Robust multi-layer wiring elements and assemblies with embedded microelectronic elements

• US 10,032,646 B2
• Filed: 09/30/2016
• Issued: 07/24/2018
• Est. Priority Date: 10/10/2007
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Oganesian, Vage, Endo, Kimitaka
• Primary Examiner(s): Graybill, David E
• Application Number:
  US15/282,255
• Publication Number:
  US 20170018440A1
• Time in Patent Office: 662 Days
• Field of Search: None
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/0355 : Metal foils
• CPC Class Codes: H05K 2201/0361 : Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
• CPC Class Codes: H05K 2201/0382 : Continuously deformed conductors
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/0384 : Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
• CPC Class Codes: H05K 2203/0733 : Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 2203/1189 : Pressing leads, bumps or a die through an insulating layer
• CPC Class Codes: H05K 3/0038 : combined with laser drilling through a metal layer
• CPC Class Codes: H05K 3/4038 : Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: H05K 3/4647 : by applying an insulating layer around previously made via studs
• CPC Class Codes: H05K 3/4652 : Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence

Abstract

An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.

Claims

1. A method of fabricating an interconnect element having a plurality of wiring layers separated from each other by at least one dielectric layer, comprising:

(a) laminating a dielectric layer, a first metal layer atop the dielectric layer, and a second metal layer atop the dielectric layer onto a base element, wherein the base element includes a third metal layer having at least portions defining a plane and a plurality of conductive protrusions extending upwardly from the plane, wherein the first metal layer includes first openings, and wherein the laminating is performed such that portions of the dielectric layer separate adjacent ones of the conductive protrusions; and

then

(b) forming second openings in the dielectric layer which are aligned with the first openings so that at least top surfaces of the conductive protrusions are exposed through the first and second openings; and

(c) plating a metal onto the exposed top surfaces of the conductive protrusions within the first and second openings to form plated features connecting the conductive protrusions with the first metal layer.

2. A method as set forth in claim 1, further comprising patterning the third metal layer to form wiring patterns after forming the plated features.

3. A method as set forth in claim 1, further comprising patterning the first metal layer to form wiring patterns after forming the plated features.

4. A method as set forth in claim 1, wherein the dielectric layer includes an uncured dielectric element and step (a) is formed by pressing the uncured dielectric element onto the third metal layer and the conductive protrusions thereon at a temperature of about 200°

C. or less and then curing the uncured dielectric element.

5. A method as set forth in claim 1, wherein during step (a), the first and third metal layers define continuous planes.

6. A method as set forth in claim 1, wherein step (a) includes laminating the first metal layer onto the base element such that the first openings therein are aligned with the conductive protrusions.

7. A method as set forth in claim 1, further comprising, patterning the second metal layer to form second conductive protrusions extending upwardly from the first metal layer.

8. A method as set forth in claim 1, further comprising etching a fourth metal layer attached to the third metal layer to form the conductive protrusions of the base element.

9. A method as set forth in claim 1, wherein the conductive protrusions include hollow conductive protrusions.

10. A method as set forth in claim 7, further comprising:

(d) laminating a second dielectric layer and a fourth metal layer atop the dielectric layer onto the first metal layer and the plurality of second conductive protrusions extending upwardly therefrom such that portions of the second dielectric layer separate adjacent ones of the second conductive protrusions;

(e) forming third openings in the second dielectric layer which expose at least top surfaces of the second conductive protrusions; and

(f) plating a metal onto the exposed surfaces of the second conductive protrusions within the third openings in the second dielectric layer to form second plated features connecting the second conductive protrusions with the fourth metal layer.

11. A method as set forth in claim 10, wherein during step (d) the first, second and fourth metal layers define continuous planes.

12. A method as set forth in claim 10, wherein during step (d), at least one of the first and fourth metal layers includes a plurality of individual traces extending in directions defining a plane.

13. A method as set forth in claim 10, wherein when the fourth metal layer is laminated with the second dielectric layer onto the first metal layer and second conductive protrusions extending therefrom in step (d), the fourth metal layer has openings aligned with the second conductive protrusions and the fourth metal layer is attached to a fifth metal layer overlying the fourth metal layer.

14. A method as set forth in claim 13, further comprising, prior to step (e), patterning the fifth metal layer to form third conductive protrusions extending upwardly from the fourth metal layer.

18. The method of claim 1, wherein during step (a) the first metal layer further includes individual wiring patterns.

15. A method of packaging a microelectronic element between wiring layers of an interconnect element having a plurality of wiring layers separated from each other by at least one dielectric layer, comprising:

forming openings through a first metal layer;

laminating a dielectric layer, the first metal layer atop the dielectric layer, and a second metal layer atop the dielectric layer onto a first element, the first element including a third metal layer having at least portions defining a plane, a plurality of conductive protrusions extending upwardly from the plane and a microelectronic element having a first face adjacent to the plane, the laminating performed such that portions of the dielectric layer separate adjacent ones of the conductive protrusions and separate the microelectronic element from the conductive protrusions, wherein the first metal layer includes first openings, at least some of the first openings being aligned with the plurality of conductive protrusions, and other of the first openings aligned with contacts at an opposed second face of the microelectronic element; and

then

forming second openings in the dielectric layer, wherein some of the second openings are aligned with the first openings aligned with the contacts so as to expose the contacts through corresponding first and second openings and wherein other of the second openings are aligned with the first openings aligned with at least the top surfaces of the conductive protrusions so as to expose the at least top surfaces of the conductive protrusions through corresponding first and second openings; and

plating a metal onto the exposed contacts and exposed surfaces of the conductive protrusions within the first and second openings to form plated features connecting the contacts and the conductive protrusions with the first metal layer.

16. A method as set forth in claim 15, wherein the third metal layer includes a thermally conductive plate attached to the first face of the microelectronic element.

19. The method of claim 15, wherein during step (b), the first metal layer further includes individual wiring patterns.

17. A method of forming an interconnect element including at least one of an active or passive component between respective wiring layers of the interconnect element having a plurality of wiring layers separated from each other by at least one dielectric layer, comprising:

laminating a dielectric layer, a first metal layer atop the dielectric layer, and a second metal layer atop the first metal layer onto a first element, the first element including a third metal layer having at least portions defining a plane, wherein a plurality of conductive protrusions extend upwardly from the plane and at least one of an active or passive component have a surface overlying the plane, wherein the first metal layer includes first openings, at least some of the first openings being aligned with contacts of the at least one of the active or passive component, and wherein other of the first openings are aligned with at least top surfaces of the conductive protrusions, the step of laminating performed such that portions of the dielectric layer separate adjacent ones of the conductive protrusions and the active or passive component from each other; and

then

forming second openings in the dielectric layer, wherein some of the second openings are aligned with the first openings aligned with the contacts so as to expose the contacts through corresponding first and second openings and wherein other of the second openings are aligned with the first openings aligned with the conductive protrusions so as to expose at least top surfaces of the conductive protrusions through corresponding first and second openings; and

plating a metal onto the exposed contacts and exposed surfaces of the conductive protrusions within the first and second openings to form plated features connecting the contacts and the conductive protrusions with the second metal layer.