Methods and systems for preventing unsafe operations

• US 10,032,659 B2
• Filed: 12/27/2013
• Issued: 07/24/2018
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: GlobalWafers Co., Ltd. (Sino-American Silicon Products Incorporated)
• Original Assignee: SunEdison, Inc.
• Inventors: Orschel, Benno, Wolfram, Mike
• Primary Examiner(s): Dao, Thuy
• Application Number:
  US14/142,533
• Publication Number:
  US 20140188261A1
• Time in Patent Office: 1,670 Days
• CPC Class Codes: G05B 19/406 characterised by monitoring or safety G05B19/19 takes precedence
• CPC Class Codes: G05B 2219/35283 Plausibility check for function, program, inhibit dangerous, unallowed program
• CPC Class Codes: G05B 2219/45031 Manufacturing semiconductor wafers
• CPC Class Codes: G05B 2219/50193 Safety in general
• CPC Class Codes: H01L 21/67288 Monitoring of warpage, curvature, damage, defects or the like

Abstract

A system for preventing an unsafe operation of at least one machine communicatively coupled to a computing device. The system includes the computing device which includes a processor coupled to a memory. The memory contains processor-executable instructions that, when executed, cause the computing device to perform the steps of storing, in the memory, a first state of a first machine of the at least one machine, generating a first pending output to be issued to the first machine, determining whether an unsafe condition would result if the first pending output is issued to the first machine in the first state, and issuing the first pending output upon determining that issuing the first pending output would not result in an unsafe condition and blocking the first pending output from being issued upon determining that issuing the first pending output would result in an unsafe condition.

Claims

1. A system for preventing an unsafe operation of a plurality of silicon wafer manufacturing machines communicatively coupled to a computing device, the system comprising said computing device, said computing device including a processor coupled to a memory, said memory containing processor-executable instructions that, when executed by said processor, cause said computing device to perform the steps of:

storing, in said memory, a first state of a first machine of the plurality of machines;

generating a first pending output to be issued to the first machine;

determining whether an unsafe condition would result if the first pending output is issued to the first machine in the first state;

issuing the first pending output upon determining that issuing the first pending output would not result in an unsafe condition; and

blocking the first pending output from being issued for a predetermined period of time upon determining that issuing the first pending output would result in an unsafe condition and issuing the first pending output after the predetermined period of time.

2. The system of claim 1, wherein the processor-executable instructions further cause said computing device to perform the steps of:

storing, in said memory, a second state of a second machine of the plurality of machines;

generating a second pending output to be issued to the second machine;

determining whether an unsafe condition would result if the first pending output is issued to the first machine in the first state and the second pending output is issued to the second machine in the second state; and

issuing the first pending output and second pending output upon determining that issuing the first pending output and second pending output would not result in an unsafe condition or blocking at least one of the first pending output and second pending output from being issued upon determining that issuing the first pending output and second pending output would result in an unsafe condition.

3. The system of claim 2, wherein said memory further includes processor-executable instructions such that blocking at least one of the first pending output and second pending output from being issued further includes blocking the second pending output for a predetermined period of time, then issuing the second pending output.

4. The system of claim 1, wherein the processor-executable instructions further cause said computing device to perform the step of storing an error indicator in said memory upon determining that issuing the first pending output would result in an unsafe condition.

5. The system of claim 1, wherein the processor-executable instructions further cause said computing device to execute a master thread and perform the steps in the master thread.

6. The system of claim 1, wherein the processor-executable instructions further cause said computing device to perform the step of storing a completion indicator in said memory.

7. The system of claim 6, wherein the processor-executable instructions further cause said computing device to perform the steps of:

executing a watchdog thread;

with the watchdog thread, determining whether the completion indicator is stored in said memory after a predetermined period of time has elapsed; and

with the watchdog thread, instructing the at least one machine to enter a safe state upon determining that the completion indicator is not stored in said memory after the predetermined period of time has elapsed.

8. The system of claim 6, wherein the processor-executable instructions further cause said computing device to perform the steps of:

executing a watchdog thread;

with the watchdog thread, determining whether the completion indicator is stored in said memory after a predetermined period of time has elapsed; and

with the watchdog thread, instructing at least one machine of the plurality of machines to enter a safe state upon determining that the completion indicator is not stored in said memory after the predetermined period of time has elapsed and blocking further pending outputs from being issued to the at least one machine.

9. A method for preventing an unsafe operation of at least one machine communicatively coupled to a computing device that is coupled to a memory, the method is performed by the computing device and comprises the steps of:

storing, in the memory, a first state of a first machine of the at least one machine;

generating a first pending output to be issued to the first machine;

determining whether an unsafe condition would result if the first pending output is issued to the first machine in the first state;

issuing the first pending output upon determining that issuing the first pending output would not result in an unsafe condition; and

blocking the first pending output from being issued for a predetermined period of time upon determining that issuing the first pending output would result in an unsafe condition, and issuing the first pending output after the predetermined period of time.

10. The method of claim 9, further comprising the steps of:

storing, in the memory, a second state of a second machine of the at least one machine;

generating a second pending output to be issued to the second machine;

determining whether an unsafe condition would result if the first pending output is issued to the first machine in the first state and the second pending output is issued to the second machine in the second state;

issuing the first pending output and second pending output upon determining that issuing the first pending output and second pending output would not result in an unsafe condition or blocking at least one of the first pending output and second pending output from being issued upon determining that issuing the first pending output and second pending output would result in an unsafe condition.

11. The method of claim 10, wherein blocking at least one of the first pending output and second pending output from being issued further includes blocking the second pending output for a predetermined period of time, then issuing the second pending output.

12. The method of claim 9, further comprising storing an error indicator in the memory upon determining that issuing the first pending output would result in an unsafe condition.

13. The method of claim 9, further comprising the step of executing a master thread and performing the steps in the master thread.

14. The method of claim 9, further comprising the step of storing a completion indicator in the memory.

15. The method of claim 14, further comprising the steps of:

executing a watchdog thread;

with the watchdog thread, determining whether the completion indicator is stored in the memory after a predetermined period of time has elapsed; and

with the watchdog thread, instructing the at least one machine to enter a safe state upon determining that the completion indicator is not stored in the memory after the predetermined period of time has elapsed.

16. The method of claim 14, further comprising the steps of:

executing a watchdog thread;

with the watchdog thread, determining whether the completion indicator is stored in the memory after a predetermined period of time has elapsed; and

with the watchdog thread, instructing the at least one machine to enter a safe state upon determining that the completion indicator is not stored in the memory after the predetermined period of time has elapsed and blocking further instructions from being issued to the at least one machine.

17. A non-transitory computer-readable storage device having processor-executable instructions embodied thereon for preventing an unsafe operation of at least one machine communicatively coupled to a computing device, the computing device having a processor coupled to a memory, wherein, when executed by said processor, the processor-executable instructions cause the computing device to perform the steps of:

storing, in the memory, a first state of a first machine of the at least one machine;

generating a first pending output to be issued to the first machine;

determining whether an unsafe condition would result if the first pending output is issued to the first machine in the first state;

issuing the first pending output upon determining that issuing the first pending output would not result in an unsafe condition; and

blocking the first pending output from being issued for a predetermined period of time upon determining that issuing the first pending output would result in an unsafe condition, and issuing the first pending output after the predetermined period of time.

18. The computer-readable storage device of claim 17, wherein the processor-executable instructions further cause the computing device to perform the steps of:

storing, in the memory, a second state of a second machine of the at least one machine;

generating a second pending output to be issued to the second machine;

determining whether an unsafe condition would result if the first pending output is issued to the first machine in the first state and the second pending output is issued to the second machine in the second state; and

issuing the first pending output and second pending output upon determining that issuing the first pending output and second pending output would not result in an unsafe condition or blocking at least one of the first pending output and second pending output from being issued upon determining that issuing the first pending output and second pending output would result in an unsafe condition.

19. The computer-readable storage device of claim 18, wherein the memory further includes processor-executable instructions such that blocking at least one of the first pending output and second pending output from being issued further includes blocking the second pending output for a predetermined period of time, then issuing the second pending output.

20. The computer-readable storage device of claim 17, wherein the processor-executable instructions further cause the computing device to perform the step of storing an error indicator in the memory upon determining that issuing the first pending output would result in an unsafe condition.