Double-side cooling type power module and producing method thereof

• US 10,032,689 B2
• Filed: 12/13/2016
• Issued: 07/24/2018
• Est. Priority Date: 10/06/2016
• Status: Active Grant

• Current Assignee: Hyundai Motor Company (Hyundai Motor Group)
• Original Assignee: Hyundai Motor Company (Hyundai Motor Group)
• Inventors: Jeon, Woo Yong, Lee, Hyun Koo, Park, Sung Min, Jang, Ki Young
• Primary Examiner(s): JUNGE, BRYAN R.
• Application Number:
  US15/377,768
• Publication Number:
  US 20180102301A1
• Time in Patent Office: 588 Days
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/29139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/33 of a plurality of layer connectors
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49537 Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/33 of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

Disclosed herein are a double-side cooling type power module and a producing method thereof. The double-side cooling type power module includes a pair of semiconductor chips disposed between an upper substrate and a lower substrate. The double-side cooling type power module includes output terminal leads configured to be disposed on a lower surface of the upper substrate and each connected to the pair of semiconductor chips, respectively; a plus terminal lead configured to be disposed at one side of an upper surface of the lower substrate to be connected to any one semiconductor chip selected from the pair of semiconductor chips; and a minus terminal lead configured to be disposed at the other side of the upper surface of the lower substrate to be connected to the other semiconductor chip of the pair of semiconductor chips.

Claims

1. A power module comprising:

an upper substrate;

a lower substrate;

a first semiconductor chip and a second semiconductor chip disposed between the upper substrate and the lower substrate;

an output terminal lead disposed under a lower surface of the upper substrate, wherein the first and second semiconductor chips are electrically connected to the output terminal lead;

a first polarity terminal lead disposed over an upper surface of the lower substrate and electrically connected to the first semiconductor chip; and

a second polarity terminal lead disposed over the upper surface of the lower substrate and electrically connected to the second semiconductor chip,

a first spacer formed between the first semiconductor chip and the output terminal lead such that the upper substrate, the output terminal lead, the first spacer, the first semiconductor chip, the first polarity terminal lead and the lower substrate are arranged in order, wherein the first spacer is braze-bonded to the output terminal lead whereas the first spacer is solder-bonded to the first semiconductor chip; and

a second spacer formed between the second semiconductor chip and the second polarity terminal lead such that the upper substrate, the output terminal lead, the second semiconductor chip, the second spacer and the second polarity terminal lead and the lower substrate are arranged in order, wherein the second spacer is braze-bonded to the second polarity terminal lead whereas the second spacer is solder-bonded to the second semiconductor chip.

2. The power module of claim 1,

wherein the lower substrate includes a ceramic layer, a first polarity terminal layer disposed over the ceramic layer and bonded to the first polarity terminal lead, and a second polarity terminal layer disposed over the ceramic layer and bonded to the second polarity terminal lead, and

wherein the first polarity terminal layer and the second polarity terminal layer are insulated from each other.

3. The power module of claim 2, wherein the first polarity terminal layer is braze-bonded to the first polarity terminal lead, and

wherein the second polarity terminal layer is braze-bonded to the second polarity terminal lead.

4. The power module of claim 1, further comprising:

a plurality of signal leads connected to the first semiconductor chip and the second semiconductor chip and configured to transmit and receive control signals.