Positional relationship among components of semiconductor device

• US 10,032,700 B2
• Filed: 01/09/2015
• Issued: 07/24/2018
• Est. Priority Date: 03/13/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Takahashi, Noriyuki
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US14/593,689
• Publication Number:
  US 20150262922A1
• Time in Patent Office: 1,292 Days
• Field of Search: 257676, 257787, 257784, 257786, 257672
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49555 : the bent parts being the outer leads
• CPC Class Codes: H01L 23/49565 : Side rails of the lead frame, e.g. with perforations, sprocket holes
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

Claims

1. A semiconductor device comprising:

a die pad including a first surface and a second surface opposite to the first surface;

a semiconductor chip including a main surface, a plurality of bonding electrodes formed on the main surface and a back surface opposite to the main surface, and mounted on the first surface of the die pad via a die bond material such that the back surface faces the first surface of the die pad, the semiconductor chip being essentially comprised a first material having a first linear expansion coefficient;

a plurality of leads electrically connected with the plurality of bonding electrodes via a plurality of wires, respectively; and

a sealing body including an upper surface located on the same side as the main surface of the semiconductor chip, a lower surface opposite to the upper surface, a first side surface located between the upper surface and the lower surface, and a second side surface located between the upper surface and the lower surface and also opposite to the first side surface, and sealing the semiconductor chip and the plurality of wires, the sealing body being essentially comprised of a second material having a second linear expansion coefficient, which is higher than the first linear expansion coefficient,

wherein each of the plurality of leads has an inner part sealed with the sealing body, and an outer part exposed from the sealing body,

wherein the outer part has;

a first part connected to the inner part and extending in a horizontal direction, which is along the upper surface of the sealing body,

a second part connected to the first part via a first bending portion that bends the outer part in a thickness direction, which is from the upper surface toward the lower surface, of the sealing body, and

a third part connected to the second part via a second bending portion that bends the outer part in the horizontal direction,

wherein the plurality of leads has;

a first lead electrically connected with a first bonding electrode of the plurality of bonding electrodes via a first wire of the plurality of wires and protruding from the first side surface of the sealing body, and

a second lead electrically connected with a second bonding electrode of the plurality of bonding electrodes via a second wire of the plurality of wires and protruding from the second side surface of the sealing body,

wherein, in cross-section view, the semiconductor chip is located between the inner part of the first lead and the inner part of the second lead,

wherein, in cross-section view, a thickness of the semiconductor chip is greater than a thickness from the second surface of the die pad to the lower surface of the sealing body, which is greater than a thickness of each of the die pad and the die bond material,

wherein, in cross-section view, a stand-off amount of each of the plurality of leads, which is a distance, in the thickness direction of the sealing body, from the lower surface of the sealing body to the third part of the outer part, is greater than 0.40 mm and less than a thickness from the upper surface of the sealing body to the lower surface of the sealing body, and

wherein, in cross-section view, the stand-off amount of each of the plurality of leads is greater than a thickness from an upper surface of the inner part of each of the plurality of leads, which is located on the same side as the main surface of the semiconductor chip, to the upper surface of the sealing body, or a thickness from a lower surface of the inner part of each of the plurality of leads, which is located on the same side as the second surface of the die pad, to the lower surface of the sealing body.

2. The semiconductor device according to claim 1,

wherein the first material is silicon, and

wherein the second material is epoxy resin.

3. The semiconductor device according to claim 1, wherein, in cross-section view, the thickness of the semiconductor chip is greater than a thickness from the main surface of the semiconductor chip to the upper surface of the sealing body.

4. The semiconductor device according to claim 1, wherein the thickness from the upper surface of the sealing body to the lower surface of the sealing body is one of 1.40 mm and 1.00 mm.

5. The semiconductor device according to claim 4, wherein the stand-off amount of each of the plurality of leads is 0.73 mm.

6. The semiconductor device according to claim 4, wherein a thickness of each of the plurality of leads is 0.125 mm or 0.15 mm.

7. The semiconductor device according to claim 6, wherein the semiconductor device is QFP (Quad Flat Package).

8. A semiconductor device comprising:

a die pad including a first surface and a second surface opposite to the first surface;

a semiconductor chip including a main surface, a plurality of bonding electrodes formed on the main surface and a back surface opposite to the main surface, and mounted on the first surface of the die pad via a die bond material such that the back surface faces the first surface of the die pad, the semiconductor chip being essentially comprised a first material having a first linear expansion coefficient;

a plurality of leads electrically connected with the plurality of bonding electrodes via a plurality of wires, respectively; and

a sealing body including an upper surface located on the same side as the main surface of the semiconductor chip, a lower surface opposite to the upper surface, a first side surface located between the upper surface and the lower surface, and a second side surface located between the upper surface and the lower surface and also opposite to the first side surface, and sealing the semiconductor chip and the plurality of wires, the sealing body being essentially comprised of a second material having a second linear expansion coefficient, which is higher than the first linear expansion coefficient,

wherein each of the plurality of leads has an inner part sealed with the sealing body, and an outer part exposed from the sealing body,

wherein the outer part has;

a first part connected to the inner part and extending in a horizontal direction, which is along the upper surface of the sealing body,

a second part connected to the first part via a first bending portion that bends the outer part in a thickness direction, which is from the upper surface toward the lower surface, of the sealing body, and

a third part connected to the second part via a second bending portion that bends the outer part in the horizontal direction,

wherein the plurality of leads has;

a first lead electrically connected with a first bonding electrode of the plurality of bonding electrodes via a first wire of the plurality of wires and protruding from the first side surface of the sealing body, and

a second lead electrically connected with a second bonding electrode of the plurality of bonding electrodes via a second wire of the plurality of wires and protruding from the second side surface of the sealing body,

wherein, in cross-section view, the semiconductor chip is located between the inner part of the first lead and the inner part of the second lead,

wherein, in cross-section view, a thickness of the semiconductor chip is greater than a thickness, from the second surface of the die pad to the lower surface of the sealing body which is greater than a thickness of each of the die pad and the die bond material,

wherein, in cross-section view, a stand-off amount of each of the plurality of leads, which is a distance, in the thickness direction of the sealing body, from the lower surface of the sealing body to the third part of the outer part, is greater than 0.40 mm and less than 1.00 mm, and

wherein, in cross-section view, the stand-off amount of each of the plurality of leads is greater than a thickness from an upper surface of the inner part of each of the plurality of leads, which is located on the same side as the main surface of the semiconductor chip, to the upper surface of the sealing body, or a thickness from a lower surface of the inner part of each of the plurality of leads, which is located on the same side as the second surface of the die pad, to the lower surface of the sealing body.

9. The semiconductor device according to claim 8,

wherein the first material is silicon, and

wherein the second material is epoxy resin.

10. The semiconductor device according to claim 8, wherein, in cross-section view, the thickness of the semiconductor chip is greater than a thickness from the main surface of the semiconductor chip to the upper surface of the sealing body.

11. The semiconductor device according to claim 8, wherein the stand-off amount of each of the plurality of leads is 0.73 mm.

12. The semiconductor device according to claim 8, wherein a thickness of each of the plurality of leads is 0.125 mm or 0.15 mm.

13. The semiconductor device according to claim 12, wherein the semiconductor device is QFP (Quad Flat Package).