Embedding thin chips in polymer

• US 10,032,709 B2
• Filed: 01/23/2017
• Issued: 07/24/2018
• Est. Priority Date: 10/09/2012
• Status: Active Grant

• Current Assignee: Medidata Solutions Incorporated (Dassault Systemes SA)
• Original Assignee: MC10, Inc.
• Inventors: Rafferty, Conor, Dalal, Mitul
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US15/412,993
• Publication Number:
  US 20170200670A1
• Time in Patent Office: 547 Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/03436 Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/036 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/8203 : Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2224/83132 : using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/8314 : Guiding structures outside the body
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/16 : Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H05K 1/0283 : Stretchable printed circuits
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/189 : characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2203/1469 : Circuit made after mounting or encapsulation of the components

Abstract

Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.

Claims

1. An apparatus comprising:

A) a substrate comprising a standoff well region, wherein;

the substrate comprises a layer of a first conductive material disposed on a layer of a flexible and stretchable polymer, and

a patterned portion of the first conductive material comprises a standoff bordering a portion of exposed flexible and stretchable polymer, thereby forming the standoff well region; and

B) a sensor disposed within the standoff well region on a portion of the exposed flexible and stretchable polymer proximate to the standoff.

2. The apparatus of claim 1, wherein the sensor is embedded in the portion of the exposed flexible and stretchable polymer proximate to the standoff.

3. The apparatus of claim 1, wherein a height of the standoff greater than or about equal to a height of the sensor.

4. The apparatus of claim 1, wherein the standoff completely surrounds the sensor.

5. The apparatus of claim 1, wherein the standoff includes at least one gap between a plurality of standoffs that define the standoff well region.

6. An apparatus comprising:

A) a substrate comprising a standoff well region, wherein;

the substrate comprises a layer of a first conductive material disposed on a layer of a flexible and stretchable polymer, and

a patterned portion of the first conductive material comprises a standoff bordering a portion of exposed flexible and stretchable polymer, thereby forming the standoff well region; and

B) an electrical interconnect disposed within the standoff well region on a portion of the exposed flexible and stretchable polymer proximate to the standoff.

7. The apparatus of claim 6, wherein the electrical interconnect is embedded in the portion of the exposed flexible and stretchable polymer proximate to the standoff.

8. The apparatus of claim 6, wherein a height of the standoff greater than or about equal to a height of the electrical interconnect.

9. The apparatus of claim 6, wherein the electrical interconnect is a stretchable serpentine interconnect.

10. The apparatus of claim 6, wherein the electrical interconnect is one or more interconnects electrically connecting a plurality of device islands.

11. The apparatus of claim 10, wherein a height of the standoff is greater than or equal to a height of the one or more electrical interconnects and the plurality of device islands.

12. The apparatus of claim 10, wherein the plurality of device islands include one or more thinned chips disposed on the flexible and stretchable polymer.

13. The apparatus of claim 10, further comprising at least one additional layer disposed on the first conductive material or on the flexible and stretchable polymer, wherein the at least one additional layer positions the one or more interconnects and the plurality of device islands at a neutral mechanical plane of the apparatus.

14. The apparatus of claim 6, wherein the standoff completely surrounds the electrical interconnect.

15. The apparatus of claim 6, wherein the standoff includes at least one gap between a plurality of standoffs that define the standoff well region.

16. A method for embedding electrical interconnects, the method comprising:

A) providing a substrate comprising a standoff well region, wherein;

the substrate comprises a layer of a first conductive material disposed on a layer of a flexible and stretchable polymer, and

a patterned portion of the first conductive material comprises a standoff bordering a portion of exposed flexible and stretchable polymer, thereby forming the standoff well region; and

B) disposing an electrical interconnect on a portion of the exposed flexible and stretchable polymer proximate to the standoff.

17. The method of claim 16, wherein the electrical interconnect is further embedded in the portion of the exposed flexible and stretchable polymer proximate to the standoff.

18. The method of claim 16, wherein the electrical interconnect is a stretchable serpentine interconnect.

19. The method of claim 16, wherein the electrical interconnect is a one or more interconnects electrically connecting a plurality of device islands.