Semiconductor structure

• US 10,032,712 B2
• Filed: 04/03/2013
• Issued: 07/24/2018
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ying-Ju, Chen, Hsien-Wei
• Primary Examiner(s): Kim, Su C
• Application Number:
  US13/855,812
• Publication Number:
  US 20140264922A1
• Time in Patent Office: 1,938 Days
• Field of Search: 257774, 257330, 257751, 257334, 257 43, 257773, 257 2, 257316, 257 4, 257 48, 257737, 257758, 257506, 257522, 257621, 257734, 257 88, 257 99, 257E21577, 257E23011, 257145, 257288, 257292, 257296, 257306, 257314, 257324, 257329, 257368, 257392, 257421, 257431, 257432, 257447, 257499, 257 5, 257532, 257668, 257698, 257755, 257760, 257777, 257 93, 438382, 438270, 438643, 438652, 438667, 438 69, 438268, 438381, 438586, 438613, 438637, 438653, 438666, 438675, 438151, 438 18, 438212, 438243, 438253, 438257, 438285, 438296, 438 3, 438303, 438396, 438399, 438424, 438427, 438 46, 438589, 438592, 438601, 438625, 438626, 438655, 438672, 438 68, 438692, 438 7, 438 8, 438 99
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.

Claims

1. A semiconductor structure, comprising:

a first metal region within at least some of a first dielectric region;

a first barrier region between the first metal region and the first dielectric region, the first barrier region including a substantially vertical sidewall;

a conductive cap region above the first metal region;

a second metal region within at least some of a second dielectric region, the second dielectric region above at least some of at least one of the first dielectric region, the conductive cap region, or the first metal region;

an etch stop layer (ESL) disposed between the first dielectric region and the second dielectric region, wherein a bottom surface of the ESL, a top surface of the first barrier region, a top surface of the first dielectric region, and a top surface of the conductive cap region are coplanar;

a via plug connecting the first metal region and the second dielectric region, the via plug extending from the second metal region through the ESL, the conductive cap region, and into the first metal region; and

a second barrier region between the second metal region and the second dielectric region and between the via plug and the second dielectric region,

wherein a substantially vertical sidewall of the second barrier region physically contacts the second metal region, the second dielectric region and the via plug,

wherein the second barrier region further includes a tapered surface extending from below a bottom surface of the conductive cap region to a horizontal surface of the second barrier region within the first metal region, the horizontal surface being perpendicular to the substantially vertical sidewall of the second barrier region, and

wherein the conductive cap region is within the first barrier region, wherein the conductive cap region includes cap sidewalls physically contacting substantially vertical sidewalls of the first barrier region and the second barrier region, wherein the cap sidewalls are aligned with sidewalls of the first metal region, and wherein the second barrier region is a uniform and conformal film.

2. The semiconductor structure of claim 1, wherein the ESL has a planar top surface.

3. The semiconductor structure of claim 1, wherein the ESL comprises carbon, silicon, nitrogen, or oxygen.

4. The semiconductor structure of claim 1, wherein a bottom portion of the via plug extends into the first metal region between about 100 Å

to about 500 Å

.

5. The semiconductor structure of claim 1, wherein the conductive cap region comprises CoWP.

6. The semiconductor structure of claim 1, wherein a tapered sidewall of a bottom portion of the via plug extends at an angle of between about 30°

to about 60°

relative to the bottom surface of the via plug.

7. The semiconductor structure of claim 1, wherein a plug taper distance of the via plug is between about 50 Å

to about 150 Å

.

8. The semiconductor structure of claim 1, wherein an entire bottom surface of the ESL is disposed along a single plane.

9. The semiconductor structure of claim 1, wherein the tapered surface of the second barrier region extends from a level below a bottom surface of the conductive cap region to a horizontal surface within the first metal region.

10. A semiconductor structure, comprising:

a first dielectric region;

a first metal region within at least some of the first dielectric region;

a first barrier region disposed between the first metal region and the first dielectric region, the first barrier region including a substantially vertical sidewall;

a cap region above at least some of the first metal region;

a second dielectric region above at least some of at least one of the first dielectric region, the cap region, or the first metal region;

an etch stop layer (ESL) between the first dielectric region and the second dielectric region;

a second metal region within at least some of the second dielectric region;

a via plug connecting the first metal region and the second dielectric region, the via plug extending from the second metal region through the ESL and the cap region and into the first metal region; and

a second barrier region between the second metal region and the second dielectric region and between the via plug and the second dielectric region,

wherein a substantially vertical sidewall of the second barrier region physically contacts the second dielectric region, the ESL, the cap region, and the first metal region,

wherein a tapered surface of the second barrier region extends from below a bottom surface of the cap region to a horizontal bottom surface within the first metal region that is perpendicular to the substantially vertical sidewall of the second barrier region, wherein the ESL has a single planar bottom surface, and wherein the cap region extends between the substantially vertical sidewall of the first barrier region and the substantially vertical sidewall of the second barrier region, and wherein the ESL is separated from the first metal region.

11. The semiconductor structure of claim 10, wherein the first dielectric region comprises a low-k dielectric material.

12. The semiconductor structure of claim 10, wherein the cap region physically contacts the substantially vertical sidewall of the first barrier region and the substantially vertical sidewall of the second barrier region.

13. The semiconductor structure of claim 12, wherein the cap region is conductive and the second barrier region is a uniform and conformal film.

14. The semiconductor structure of claim 10, wherein a bottom portion of the via plug extends into the first metal region between about 200 Å

to about 400 Å

.

15. The semiconductor structure of claim 14, wherein a tapered sidewall of the bottom portion of the via plug extends at an angle of between about 40°

to about 50°

relative to the bottom surface of the via plug.

16. The semiconductor structure of claim 14, wherein a plug taper distance of the via plug is between about 80 Å

to about 120 Å

.

17. The semiconductor structure of claim 10, wherein the ESL includes carbon, silicon, nitrogen, or oxygen.

18. The semiconductor structure of claim 10, wherein the ESL has a single planar top surface.

19. A method for forming a semiconductor structure, comprising:

forming a first metal region within at least some of a first dielectric region;

forming a first barrier region between the first metal region and the first dielectric region;

forming a conductive cap region above at least some of the first metal region such that the conductive cap region, the first barrier region, and the first dielectric region have respective top surfaces being coplanar;

forming an etch stop layer (ESL) above the conductive cap region, the first metal region, and the first dielectric region such that the ESL has a single planar bottom surface that is coplanar with a top surface of the first dielectric region, a top surface of the conductive cap region, and a top surface of the first barrier region, wherein the ESL is separated from the first metal region;

forming a second dielectric region above at least some of at least one of the first dielectric region, the conductive cap region, and the ESL;

forming a first trench opening by removing at least some of the second dielectric region, wherein the first trench opening has a substantially vertical profile extending through the second dielectric region, the ESL, the conductive cap region, and a portion of the first metal region below the conductive cap region, and wherein the first trench opening has a tapered profile extending from a level below a bottom surface of the conductive cap region into the first metal region, and wherein the tapered profile terminates at a horizontal surface of the first trench opening within the first metal region;

forming a first via opening within the first metal region by removing at least some of the second dielectric region, the ESL, the conductive cap region, or the first metal region;

forming uniformly and conformally a second barrier region within the first trench opening and the first via opening such that a substantially vertical surface of the second barrier region physically contacts the second dielectric region, the ESL, the conductive cap region, and the first metal region;

forming a via plug within the first via opening; and

forming a second metal region within the first trench opening.

20. The method of claim 19, wherein the second barrier region physically contacts the via plug and the second metal region.