Trench MOSFET device and the preparation method thereof

• US 10,032,728 B2
• Filed: 06/30/2016
• Issued: 07/24/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Wang, Xiaobin, Bobde, Madhur, Thorup, Paul
• Primary Examiner(s): Dinke, Bitew
• Application Number:
  US15/197,780
• Publication Number:
  US 20180005959A1
• Time in Patent Office: 754 Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. The trench MOSFET device comprises a semiconductor substrate of a first conductivity type. The semiconductor substrate has a plurality of first trenches arranged side by side in a first preset area of the semiconductor substrate extending along a first direction and a plurality of second trenches arranged side by side in a second preset area of the semiconductor substrate extending along a second direction perpendicular to the first direction. A control gate is formed in each of the pluralities of first and second trenches. A body region of a second conductivity type is formed at a top portion of the semiconductor substrate near sidewalls of the pluralities of first and second trenches. A source region of the first conductivity type is formed on a top portion of the body region.

Claims

1. A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising:

a semiconductor substrate of a first conductivity type;

a plurality of first trenches arranged side by side in a first stripe layout in a first preset area of the semiconductor substrate, the plurality of first trenches extending along a first direction; and

a plurality of second trenches arranged side by side in a second stripe layout in a second preset area of the semiconductor substrate, the plurality of second trenches extending along a second direction perpendicular to the first direction;

wherein a respective control gate is located in each of the plurality of first trenches and the plurality of second trenches;

a body region of a second conductivity type is formed on a top portion of the semiconductor substrate near sidewalls of the plurality of first trenches and the plurality of second trenches; and

a source region of the first conductivity type is formed on a top portion of the body region;

wherein a first portion of the source region is along sidewalls of the plurality of first trenches and a second portion of the source region is along sidewalls of the plurality of second trenches.

2. The trench MOSFET device of claim 1, wherein the trench MOSFET device is a square chip;

the first direction is parallel to a pair of opposite sides of the square chip;

and the second direction is parallel to another pair of opposite sides of the square chip.

3. The trench MOSFET device of claim 1, wherein an end of at least one selected first trench of the plurality of first trenches is directly connected to a selected second trench of the plurality of second trenches;

and

wherein a length of the selected second trench is equal to a length of an adjacent trench of the selected second trench of the plurality of second trenches.

4. The trench MOSFET device of claim 1, wherein contact trenches are formed in mesa regions between adjacent first trenches of the plurality of first trenches and between adjacent second trenches of the plurality of second trenches;

and wherein the contact trenches are filled with a metal material.

5. The trench MOSFET device of claim 1, wherein the first preset area excludes the plurality of second trenches and the second preset area excludes the plurality of first trenches.

6. The trench MOSFET device of claim 1, wherein each of the plurality of first trenches and the plurality of second trenches comprises a respective control gate located at a top portion of the trench MOSFET device and a respective shield gate located at a bottom portion of the trench MOSFET device;

and wherein the respective control gate and the respective shield gate is isolated by a respective insulation interlayer.

7. The trench MOSFET device of claim 1, wherein an end of at least one selected first trench of the plurality of first trenches is connected to a selected second trench of the plurality of second trenches and wherein a selected control gate located in the at least one selected first trench of the plurality of first trenches is directly connected to another selected control gate located in the selected second trench of the plurality of second trenches.

8. A trench metal-oxide-semiconductor field-effect transistor (MOSFET) strip layout wafer comprises

a plurality of first trenches arranged side by side with a first stripe layout extending along a first direction in a first portion of a first MOSFET chip on the trench MOSFET strip layout wafer;

and

a plurality of second trenches arranged side by side with a second stripe layout extending along a second direction in a second portion of a second MOSFET chip on the trench MOSFET strip layout wafer;

wherein the first direction is perpendicular to the second direction;

wherein a semiconductor substrate of the first MOSFET chip is of a first conductivity type;

wherein a body region of the first MOSFET chip is of a second conductivity type and the body region is formed on a top portion of the semiconductor substrate; and

wherein a source region of the first MOSFET chip is of the first conductivity type and the source region is formed on a top portion of the body region;

wherein a first portion of the source region is along sidewalls of the plurality of first trenches and a second portion of the source region is along sidewalls of the plurality of second trenches.

9. The trench MOSFET strip layout wafer of claim 8, wherein a first selected MOSFET chip of two adjacent MOSFET chips on the trench MOSFET strip layout wafer has trenches extending along the first direction;

and wherein a second selected MOSFET chip of the two adjacent MOSFET chips on the trench MOSFET strip layout wafer has trenches extending along the second direction.

10. The trench MOSFET stripe layout wafer of claim 8, wherein a plurality of MOSFET chips are arranged on the trench MOSFET stripe layout wafer in an array comprising columns formed by a first plurality of MOSFET chips arranged alternately with columns formed by a second plurality of MOSFET chips;

wherein the first plurality of MOSFET chips comprise the trench MOSFET stripe layout extends along the first direction and the second plurality of MOSFET chips comprise the trench MOSFET stripe layout extends along the second direction.

11. The trench MOSFET stripe layout wafer of claim 8, wherein a respective control gate is located in each of the plurality of first trenches and the plurality of second trenches.

12. A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising:

a semiconductor substrate of a first conductivity type;

a plurality of first trenches arranged side by side in a first stripe layout in a first preset area of the semiconductor substrate, the plurality of first trenches extending along a first direction; and

a plurality of second trenches arranged side by side in a second stripe layout in a second preset area of the semiconductor substrate, the plurality of second trenches extending along a second direction perpendicular to the first direction;

wherein a respective control gate is located in each of the plurality of first trenches and the plurality of second trenches;

a body region of a second conductivity type is formed on a top portion of the semiconductor substrate near sidewalls of the plurality of first trenches and the plurality of second trenches; and

a source region of the first conductivity type is formed on a top portion of the body region;

wherein a first portion of the source region is along sidewalls of the plurality of first trenches and a second portion of the source region is along sidewalls of the plurality of second trenches; and

wherein a top metal layer disposed atop the trench MOSFET device contacts mesa regions between adjacent first trenches of the plurality of first trenches and between adjacent second trenches of the plurality of second trenches.

13. The trench MOSFET device of claim 12, wherein the trench MOSFET device is a square chip;

the first direction is parallel to a pair of opposite sides of the square chip; and

the second direction is parallel to another pair of opposite sides of the square chip.

14. The trench MOSFET device of claim 12, wherein an end of at least one selected first trench of the plurality of first trenches is directly connected to a selected second trench of the plurality of second trenches;

wherein a length of the selected second trench is equal to a length of an adjacent trench of the selected second trench of the plurality of second trenches.

15. The trench MOSFET device of claim 12, wherein contact trenches are formed in mesa regions between adjacent first trenches of the plurality of first trenches and between adjacent second trenches of the plurality of second trenches;

and

wherein the contact trenches are filled with a metal material.

16. The trench MOSFET device of claim 12, wherein the first preset area excludes the plurality of second trenches and the second preset area excludes the plurality of first trenches.

17. The trench MOSFET device of claim 12, wherein each of the plurality of first trenches and the plurality of second trenches comprises a respective control gate located at a top portion of the trench MOSFET device and a respective shield gate located at a bottom portion of the trench MOSFET device;

and wherein the respective control gate and the respective shield gate is isolated by a respective insulation interlayer.

18. The trench MOSFET device of claim 12, wherein an end of at least one selected first trench of the plurality of first trenches is connected to a selected second trench of the plurality of second trenches and wherein a selected control gate located in the at least one selected first trench of the plurality of first trenches is directly connected to another selected control gate located in the selected second trench of the plurality of second trenches.