Semiconductor device having field insulation layer between two fins

• US 10,032,864 B2
• Filed: 10/13/2016
• Issued: 07/24/2018
• Est. Priority Date: 01/06/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Min, Kyung Seok, Gwon, Mi Gyeong, Nam, Seong Jin, Sung, Sug Hyun, Song, Young Hoon, Oh, Young Mook
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US15/292,515
• Publication Number:
  US 20170194426A1
• Time in Patent Office: 649 Days
• CPC Class Codes: H01J 37/32192 Microwave generated discharge H01J37/32357, H01J37/32366, H01J37/32394, H01J37/32403 take precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

Semiconductor devices are provided. The semiconductor device includes a first fin and a second fin on a substrate and a field insulation layer between the first fin and the second fin. The field insulation layer include a first insulation layer and a second insulation layer on the first insulation layer and connected to the first insulation layer. The second insulation layer is wider than the first insulation layer. A ratio of a top width to a bottom width of each of the first fin and the second fin exceeds 0.5.

Claims

1. A semiconductor device, comprising:

a first fin and a second fin on a substrate; and

a field insulation layer between the first fin and the second fin, and including a first insulation layer and a second insulation layer on the first insulation layer and connected to the first insulation layer, the second insulation layer having a width wider than a width of the first insulation layer,

wherein a ratio of a top width to a bottom width of each of the first fin and the second fin exceeds 0.5, and

wherein the second insulation layer includes a bottom surface having a second width, and a top surface facing the bottom surface and having a first width, and the second width being wider than the first width.

2. The semiconductor device as claimed in claim 1, wherein the second insulation layer includes a curved sidewall connecting the top surface and the bottom surface.

3. The semiconductor device as claimed in claim 1, further comprising a gate formed on the first fin, and a dummy gate formed on the field insulation layer.

4. The semiconductor device as claimed in claim 3, further comprising an elevated source/drain formed in the first fin between the gate and the dummy gate.

5. The semiconductor device as claimed in claim 4, wherein the second insulation layer contacts the source/drain.

6. The semiconductor device as claimed in claim 5, wherein a part of the source/drain is disposed beneath the second insulation layer.

7. The semiconductor device as claimed in claim 1, wherein a top surface of the second insulation layer and a top surface of the first fin are disposed on a same plane.

8. A semiconductor device, comprising:

a first fin and a second fin protruding on a substrate and including respective longer sides and shorter sides, the shorter side of the first fin and the shorter side of the second fin being spaced apart from each other to face each other;

a field insulation layer extending between the shorter side of the first fin and the shorter side of the second fin;

a gate extending on the first fin to intersect the first fin;

a dummy gate on the field insulation layer; and

a source/drain in the first fin between the gate and the dummy gate,

wherein each of the first fin and the second fin has a ratio of a top width to a bottom width measured along the shorter side of each of the first fin and the second fin exceeds 0.5,

wherein the field insulation layer includes a first insulation layer and a second insulation layer formed on the first insulation layer and having a width wider than a width of the first insulation layer, and

wherein the second insulation layer includes a bottom surface having a second width, and a top surface facing the bottom surface and having a first width, and the second width is greater than the first width.

9. The semiconductor device as claimed in claim 8, wherein the second insulation layer includes a curved sidewall connecting the top surface and the bottom surface.

10. The semiconductor device as claimed in claim 8, wherein a part of the source/drain is disposed beneath the second insulation layer.

11. The semiconductor device as claimed in claim 8, wherein the second insulation layer contacts the source/drain.

12. A semiconductor device, comprising:

a first fin and a second fin protruding from a substrate and including respective longer sides and shorter sides, the shorter side of the first fin and the shorter side of the second fin being spaced apart from each other to face each other;

a field insulation layer between the shorter side of the first fin and the shorter side of the second fin, the field insulation layer including a first insulation layer and a second insulation layer on the first insulation layer;

a gate on the first fin to intersect the first fin;

a dummy gate on the field insulation layer; and

a source/drain in the first fin between the gate and the dummy gate,

wherein the second insulation layer is wider than the first insulation layer and a portion of the source/drain is below the second insulation layer, and

wherein the second insulation layer includes a bottom surface having a second width, and a top surface facing the bottom surface and having a first width, and the second width being greater than the first width.

13. The semiconductor device as claimed in claim 12, wherein an upper surface of the second insulation layer is wider than the dummy gate.

14. The semiconductor device as claimed in claim 12, wherein an upper surface of the second insulation layer is wider than the first fin.

15. The semiconductor device as claimed in claim 12, wherein the first fin and the second fin contact the first insulation layer.

16. The semiconductor device as claimed in claim 12, wherein a portion of the first insulation layer extends beyond the shorter sides of the first and second fins.