Semiconductor device with a semiconductor via and laterally connected electrode

• US 10,032,878 B2
• Filed: 09/23/2011
• Issued: 07/24/2018
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meiser, Andreas Peter, Zundel, Markus
• Primary Examiner(s): Chen, David
• Application Number:
  US13/241,771
• Publication Number:
  US 20130075814A1
• Time in Patent Office: 2,496 Days
• Field of Search: 257328, 257773, 257774
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a semiconductor body having a first surface and a second surface, at least one electrode arranged in at least one trench extending from the first surface into the semiconductor body, and a semiconductor via extending in a vertical direction of the semiconductor body within the semiconductor body to the second surface. The semiconductor via is electrically insulated from the semiconductor body by a via insulation layer. The at least one electrode extends in a first lateral direction of the semiconductor body through the via insulation layer and is electrically connected to the semiconductor via.

Claims

1. A semiconductor transistor device, comprising:

a semiconductor body having a first surface and a second surface;

at least one gate electrode arranged in at least one trench extending from the first surface into the semiconductor body;

a semiconductor via extending in a vertical direction of the semiconductor body within the semiconductor body to the second surface, the semiconductor via being electrically insulated from the semiconductor body by a via insulation layer wherein the via insulation layer is perpendicular to the first surface; and

wherein the at least one gate electrode extends in the semiconductor body in a first lateral direction of the semiconductor body toward the semiconductor via and through the via insulation layer into the semiconductor via,

wherein the semiconductor via comprises the same crystalline structure and semiconductor material as the surrounding semiconductor body,

wherein the at least one gate electrode comprises a material different from the semiconductor via material, or the at least one gate electrode comprises a crystalline structure different from the semiconductor via crystalline structure,

wherein the semiconductor transistor device further comprises;

a source region, a body region, a drift region and a drain region, the body region being arranged between the source region and the drift region and the drift region being arranged between the body region and the drain region,

wherein the source region, the body region, the drift region, and the drain region are arranged in the semiconductor body,

wherein the source region and the drain region are spaced apart in the vertical direction of the semiconductor body;

a source electrode arranged on the first surface and electrically connected to the source region;

a drain electrode arranged on the second surface and electrically connected to the drain region; and

a gate dielectric dielectrically insulating the at least one gate electrode from the source region and the body region.

2. The semiconductor transistor device of claim 1, wherein the drift region and the drain region have the same doping type.

3. The semiconductor transistor device of claim 1, wherein the drift region and the drain region have complementary doping types.

4. The semiconductor transistor device of claim 1, further comprising:

a field electrode arranged in the at least one trench below the at least one gate electrode with respect to the first surface and dielectrically insulated from the at least one gate electrode; and

a field electrode dielectric dielectrically insulating the field electrode from the semiconductor body.

5. The semiconductor transistor device of claim 4, wherein the field electrode in the first lateral direction is arranged distant to the via insulation layer.

6. The semiconductor transistor device of claim 1, wherein the semiconductor via further comprises a contact region electrically contacted by the at least one gate electrode, the contact region having a higher doping concentration than regions of the semiconductor via adjoining the contact region.

7. The semiconductor transistor device of claim 1, further comprising a plurality of transistor cells, each cell comprising a source zone, a body zone and a gate electrode.

8. The semiconductor transistor device according to claim 1, wherein the at least one gate electrode is electrically connected to a sensor integrated in the semiconductor body in a region of the first surface.

9. The semiconductor transistor device of claim 8, wherein the sensor is one of a temperature sensor or a current sensor.

10. The semiconductor transistor device of claim 1, further comprising at least two gate electrodes and at least two semiconductor vias, each of the gate electrodes being connected to one of the semiconductor vias.

11. The semiconductor transistor device of claim 1, wherein the source electrode includes an electrode section extending through the source region and into the body region.

12. A semiconductor transistor device, comprising:

a semiconductor body having a first surface and a second surface;

at least one gate electrode arranged in at least one trench extending from the first surface into the semiconductor body;

a semiconductor via extending in a vertical direction of the semiconductor body within the semiconductor body to the second surface, the semiconductor via being electrically insulated from the semiconductor body by a via insulation layer wherein the via insulation layer is perpendicular to the first surface; and

wherein the at least one gate electrode extends in the semiconductor body in a first lateral direction of the semiconductor body toward the semiconductor via and through the via insulation layer into the semiconductor via,

wherein the semiconductor via comprises the same crystalline structure and semiconductor material as the surrounding semiconductor body,

wherein the at least one gate electrode comprises a material different from the semiconductor via material, or the at least one gate electrode comprises a crystalline structure different from the semiconductor via crystalline structure,

wherein the semiconductor body includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate,

wherein the semiconductor transistor device further comprises;

a source region, a body region, a drift region and a drain region, the body region being arranged between the source region and the drift region and the drift region being arranged between the body region and the drain region,

wherein the source region, the body region, the drift region, and the drain region are arranged in the semiconductor body,

wherein the source region and the drain region are spaced apart in the vertical direction of the semiconductor body;

a source electrode arranged on the first surface and electrically connected to the source region;

a drain electrode arranged on the second surface and electrically connected to the drain region; and

a gate dielectric dielectrically insulating the at least one gate electrode from the source region and the body region.