Fully capacitive coupled input choppers

• US 10,033,369 B2
• Filed: 09/21/2015
• Issued: 07/24/2018
• Est. Priority Date: 12/14/2011
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Huijsing, Johan Hendrik, Fan, Qinwen, Makinwa, Kofi Afolabi Anthony
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): O TOOLE, COLLEEN J
• Application Number:
  US14/860,423
• Publication Number:
  US 20160013787A1
• Time in Patent Office: 1,037 Days
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 3/393 with field-effect devices
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03K 17/08104 in field-effect transistor switches H03K17/0812, H03K17/0814 take precedence
• CPC Class Codes: H03M 3/34 by chopping
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/452 with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input

Abstract

A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.

Claims

1. A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage, comprising:

providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input;

providing an output chopper;

capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper;

capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being capacitively coupled to the gates of the first and second transistors and the second phase being capacitively coupled to the gates of the third and fourth transistors; and

,

providing protection of the gates of the first through fourth transistors from being destroyed by excessive voltages when a negative common mode voltage surge occurs on the inputs Vinp and Vinn, by coupling the gates of the first and third transistors to the input Vinp, and coupling the gates of the second and fourth transistors to the input Vinn;

providing protection for the first through fourth transistors against being destroyed by a negative common mode input voltage step;

wherein the first through fourth transistors are MOS transistors, and wherein the sources of the first and third transistors are coupled to the Vinp input, the sources of the second and fourth transistors are coupled to the Vinn input, the drains of the first and fourth transistors are coupled to input chopper output Voutp and the drains of the second and third transistors being coupled to the input chopper output Voutn.

2. The method of claim 1 wherein the coupling the gates of the first and third transistors to the input Vinp comprises capacitively coupling a diode connected fifth transistor between ground and the input Vinp, and coupling first replica transistors to the gates of the first and third transistors, the first replica transistors replicating a conduction state of the diode connected fifth transistor to turn on the first replica transistors when a negative surge on the input Vinp reverses the voltage across the diode connected fifth transistor, and wherein the coupling the gates of the second and fourth transistors to the input Vinn comprises capacitively coupling a diode connected sixth transistor between ground and the input Vinn, and coupling second replica transistors to the gates of the second and fourth transistors, the second replica transistors replicating a conduction state of the diode connected sixth transistor to turn on when a negative surge on the input Vinn reverses the voltage across the diode connected sixth transistor.

3. The method of claim 2 further comprising providing protection of the first through fourth transistors from excessive drain source voltages by coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diodes of the first and second transistors.