Programmable logic elements and methods of operating the same

• US 10,033,383 B1
• Filed: 03/20/2017
• Issued: 07/24/2018
• Est. Priority Date: 03/20/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Richter, Ralf, Duenkel, Stefan, Beyer, Sven
• Primary Examiner(s): White, Dylan
• Application Number:
  US15/463,316
• Time in Patent Office: 491 Days
• Field of Search: 326 37- 41, 326 47
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/018585 programmable
• CPC Class Codes: H03K 19/185 using dielectric elements with variable dielectric constant, e.g. ferro-electric capacitors

Abstract

In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.

Claims

1. A programmable logic element, comprising

a P-type ferroelectric transistor element having a first gate terminal and first and second channel terminals;

and

an N-type ferroelectric transistor element having a second gate terminal and third and fourth channel terminals, wherein said first gate terminal, said first channel terminal and said second channel terminal of said P-type ferroelectric transistor are electrically connected in parallel with said second gate terminal, said third channel terminal and said fourth channel terminal of said N-type ferroelectric transistor element, respectively, and wherein a first threshold voltage of said P-type ferroelectric transistor element and a second threshold voltage of said N-type ferroelectric transistor element are substantially symmetric to each other in a non-polarized state.

2. The programmable logic element of claim 1, wherein said logic element has a P-type functional behavior when said P-type transistor element and said N-type transistor element are in a first polarized state.

3. The programmable logic element of claim 2, wherein said logic element has an N-type functional behavior when said P-type transistor element and said N-type transistor element are in a second polarized state that is inverse to said first polarized state.

4. The programmable logic element of claim 3, wherein said first threshold voltage of said P-type ferroelectric transistor element in said non-polarized state is adapted to be shiftable to a level that is less than a negative supply voltage when said P-type ferroelectric transistor element is polarized into said second polarized state.

5. The programmable logic element of claim 4, wherein said first threshold voltage of said P-type ferroelectric transistor element in said non-polarized state is further adapted to be shiftable to a desired P-type operating threshold voltage when said P-type ferroelectric transistor element is polarized into said first polarized state.

6. The programmable logic element of claim 3, wherein said second threshold voltage of said N-type ferroelectric transistor element in said non-polarized state is adapted to be shiftable to a desired N-type threshold voltage when said N-type ferroelectric transistor element is polarized into said second polarized state.

7. The programmable logic element of claim 6, wherein said second threshold voltage of said N-type ferroelectric transistor element in said non-polarized state is further adapted to be shiftable above a positive supply voltage when said N-type ferroelectric transistor element is polarized into said first polarized state.

8. The logic element of claim 1, wherein said P-type ferroelectric transistor element and said N-type ferroelectric transistor element are provided in a semiconductor layer of a semiconductor device laterally separated from each other by an isolation structure.

9. A transistor type circuit element in a semiconductor device, the transistor type circuit element comprising:

a P-type ferroelectric transistor element that is adapted to have a first threshold voltage;

an N-type ferroelectric transistor element that is adapted to have a second threshold voltage, wherein said first and second threshold voltages are substantially symmetric to each other in a non-polarized state;

a channel region connecting at one end thereof to a first channel terminal and at a second end thereof to a second channel terminal; and

a control electrode formed so as to enable control of current flow through said channel region, wherein said transistor type circuit element is configured to have a threshold voltage that is adapted to be shiftable to a first value wherein said transistor type circuit element exhibits substantially P-type characteristic current flow behavior in said channel region and shiftable to a second value wherein said transistor type circuit element exhibits substantially N-type characteristic current flow behavior.

10. The transistor type circuit element of claim 9, wherein said transistor type circuit element is further adapted to enable shifting of said threshold voltage of said transistor type circuit element to said first and second values by establishing a first polarized state and a second polarized state, respectively, in said control electrode.

11. The transistor type circuit element of claim 9, wherein a first channel region of said P-type ferroelectric transistor element is connected in parallel to a second channel region of said N-type ferroelectric transistor element so as to form said channel region.

12. The transistor type circuit element of claim 9, wherein a first channel terminal and a second channel terminal of said P-type ferroelectric transistor element are connected in parallel to a first channel terminal and a second channel terminal of said N-type ferroelectric transistor element so as to form said first and second channel terminals of said circuit element.

13. The transistor type circuit element of claim 9, wherein said first threshold voltage of said P-type ferroelectric transistor element and said second threshold voltage of said N-type ferroelectric transistor element are shiftable beyond a negative and a positive operating voltage, respectively.

14. A method of operating a logic element, the method comprising:

connecting a P-type transistor element having a first threshold voltage and an N-type transistor element having a second threshold voltage in parallel, said first and second threshold voltages being substantially symmetric to each other in a non-polarized state;

operating said parallel-connected P-type transistor element and N-type transistor element on the basis of a common control signal; and

adjusting a current characteristic of said parallel-connected P-type transistor element and said N-type transistor element by commonly shifting said first threshold voltage of said P-type transistor element and said second threshold voltage of said N-type transistor element.

15. The method of claim 14, wherein said current characteristic is adjusted in a non-volatile manner.

16. The method of claim 14, wherein adjusting said current characteristic comprises establishing a reconfigurable polarized state in said P-type transistor element and said N-type transistor element.

17. The method of claim 14, further comprising adjusting base values of said first and second threshold voltages by adjusting a dopant profile of said P-type transistor element and said N-type transistor element, respectively.

18. The method of claim 17, wherein a difference of said base values is adjusted to approximately 80 percent of a target operating voltage of a normal operation.