Adaptive clocking scheme
First Claim
Patent Images
1. A system, comprising:
- a first functional block;
a first latch circuit coupled to an output of the first functional block and configured to receive a system clock;
a second functional block;
a second latch circuit coupled to an input of the second functional block and configured to receive the system clock;
a logic path that couples an output of the first latch circuit and an input of the second latch circuit;
a clock path having a first endpoint and a second endpoint, the first endpoint and the second endpoint being coupled to an input of the first latch circuit and a second input of the second latch circuit, respectively; and
a feedback path between the second endpoint of the clock path and the first endpoint of the clock path.
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Abstract
Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
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Citations
21 Claims
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1. A system, comprising:
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a first functional block; a first latch circuit coupled to an output of the first functional block and configured to receive a system clock; a second functional block; a second latch circuit coupled to an input of the second functional block and configured to receive the system clock; a logic path that couples an output of the first latch circuit and an input of the second latch circuit; a clock path having a first endpoint and a second endpoint, the first endpoint and the second endpoint being coupled to an input of the first latch circuit and a second input of the second latch circuit, respectively; and a feedback path between the second endpoint of the clock path and the first endpoint of the clock path. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method, comprising:
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coupling an output of a first functional block to a first latch circuit; coupling an input of a second functional block to a second latch circuit; coupling a system clock to the first latch circuit and the second latch circuit; coupling, using a logic path, an output of the first latch circuit and an input of the second latch circuit; coupling a first endpoint of a clock path to an input of the first latch circuit; coupling a second endpoint of the clock path to a second input of the second latch circuit; and coupling, using a feedback path, the second endpoint of the clock path and the first endpoint of the clock path. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A system, comprising:
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a first functional block; a first latch circuit, coupled to an output of the first functional block and configured to receive a system clock; a second functional block; a second latch circuit, coupled to an input of the second functional block and configured to receive the system clock; a logic path that couples an output of the first latch circuit and an input of the second latch circuit; a clock path having a first endpoint and a second endpoint, the first endpoint and the second endpoint being coupled to an input of the first latch circuit and a second input of the second latch circuit, respectively; and a feedback path between the second endpoint and the first endpoint, wherein the clock path and the feedback path are configured and arranged to form an oscillator circuit, the oscillator circuit being configured to provide an output signal having an output frequency that is based on a propagation delay of the clock path.
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Specification