Adaptive clocking scheme

• US 10,033,391 B2
• Filed: 04/11/2016
• Issued: 07/24/2018
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Penzes, Paul, Fullerton, Mark
• Primary Examiner(s): Choudhury, Zahid
• Application Number:
  US15/095,439
• Publication Number:
  US 20160226498A1
• Time in Patent Office: 834 Days
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

Claims

1. A system, comprising:

a first functional block;

a first latch circuit coupled to an output of the first functional block and configured to receive a system clock;

a second functional block;

a second latch circuit coupled to an input of the second functional block and configured to receive the system clock;

a logic path that couples an output of the first latch circuit and an input of the second latch circuit;

a clock path having a first endpoint and a second endpoint, the first endpoint and the second endpoint being coupled to an input of the first latch circuit and a second input of the second latch circuit, respectively; and

a feedback path between the second endpoint of the clock path and the first endpoint of the clock path.

2. The system of claim 1, further comprising:

a clock module configured to generate the system clock and to provide the system clock to the first latch circuit.

3. The system of claim 2, wherein the clock module is configured to send the system clock over the clock path to the second latch circuit.

4. The system of claim 1, wherein the clock path and the feedback path form a ring oscillator circuit.

5. The system of claim 4, wherein an output frequency of the ring oscillator circuit is a function of a propagation delay of the clock path.

6. The system of claim 5, wherein the output frequency of the ring oscillator circuit is proportional to a propagation delay of a fraction of the clock path.

7. The system of claim 5, wherein the output frequency of the ring oscillator circuit is configured to vary according to changes in supply voltage, thereby adjusting a frequency of the system clock based on supply voltage variations.

8. The system of claim 1, wherein a frequency of the system clock is configured to be a function of a propagation delay of the clock path.

9. The system of claim 8, wherein the propagation delay of the clock path is configured to be equal to a propagation delay of the logic path.

10. The system of claim 8, wherein the frequency of the system clock is configured to vary according to temperature, process, and voltage variations of the propagation delay of the clock path.

11. A method, comprising:

coupling an output of a first functional block to a first latch circuit;

coupling an input of a second functional block to a second latch circuit;

coupling a system clock to the first latch circuit and the second latch circuit;

coupling, using a logic path, an output of the first latch circuit and an input of the second latch circuit;

coupling a first endpoint of a clock path to an input of the first latch circuit;

coupling a second endpoint of the clock path to a second input of the second latch circuit; and

coupling, using a feedback path, the second endpoint of the clock path and the first endpoint of the clock path.

12. The method of claim 11, further comprising:

generating the system clock using a clock module; and

providing the system clock to the first latch circuit using the clock module.

13. The method of claim 12, further comprising:

transmitting the system clock over the clock path to the second latch circuit.

14. The method of claim 11, further comprising:

forming a ring oscillator based on the clock path and the feedback path.

15. The method of claim 14, further comprising:

configuring an output frequency of the ring oscillator to be a function of a propagation delay of the clock path.

16. The method of claim 15, further comprising:

configuring the output frequency of the ring oscillator to be proportional to a propagation delay of a fraction of the clock path.

17. The method of claim 15, further comprising:

varying the output frequency of the ring oscillator according to changes in a supply voltage, thereby adjusting a frequency of the system clock based on variations in the supply voltage.

18. The method of claim 11, further comprising:

configuring a frequency of the system clock to be a function of a propagation delay of the clock path.

19. The method of claim 18, further comprising:

configuring the propagation delay of the clock path to be equal to a propagation delay of the logic path.

20. The method of claim 18, further comprising:

configuring the frequency of the system clock to vary according to temperature, process, and voltage variations of the propagation delay of the clock path.

21. A system, comprising:

a first functional block;

a first latch circuit, coupled to an output of the first functional block and configured to receive a system clock;

a second functional block;

a second latch circuit, coupled to an input of the second functional block and configured to receive the system clock;

a logic path that couples an output of the first latch circuit and an input of the second latch circuit;

a clock path having a first endpoint and a second endpoint, the first endpoint and the second endpoint being coupled to an input of the first latch circuit and a second input of the second latch circuit, respectively; and

a feedback path between the second endpoint and the first endpoint,

wherein the clock path and the feedback path are configured and arranged to form an oscillator circuit, the oscillator circuit being configured to provide an output signal having an output frequency that is based on a propagation delay of the clock path.