Enabling a non-core domain to control memory bandwidth in a processor
First Claim
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1. A processor comprising:
- a plurality of cores of the processor, a first core of the plurality of cores to operate at a first voltage and a second core of the plurality of cores to operate at a second voltage, the second voltage independent of the first voltage;
the first core of the plurality of cores to be associated with a first frequency and the second core of the plurality of cores to be associated with a second frequency, wherein the first and second frequencies may be different from each other;
a graphics unit of the processor, wherein a driver of the graphics unit is to control execution on the graphics unit;
an interconnect of the processor to couple the first core of the plurality of cores, the second core of the plurality of cores and the graphics unit to a memory external to the processor; and
a power controller tocontrol a frequency of the interconnect based at least in part on a frequency of the graphics unit,wherein the graphics unit is operable at a first plurality of frequencies and the interconnect is operable at a second plurality of frequencies, andthe power controller is to update the frequency of the interconnect to another one of the second plurality of frequencies based at least in part on the frequency of the graphics unit.
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Abstract
In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
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Citations
20 Claims
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1. A processor comprising:
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a plurality of cores of the processor, a first core of the plurality of cores to operate at a first voltage and a second core of the plurality of cores to operate at a second voltage, the second voltage independent of the first voltage; the first core of the plurality of cores to be associated with a first frequency and the second core of the plurality of cores to be associated with a second frequency, wherein the first and second frequencies may be different from each other; a graphics unit of the processor, wherein a driver of the graphics unit is to control execution on the graphics unit; an interconnect of the processor to couple the first core of the plurality of cores, the second core of the plurality of cores and the graphics unit to a memory external to the processor; and a power controller to control a frequency of the interconnect based at least in part on a frequency of the graphics unit, wherein the graphics unit is operable at a first plurality of frequencies and the interconnect is operable at a second plurality of frequencies, and the power controller is to update the frequency of the interconnect to another one of the second plurality of frequencies based at least in part on the frequency of the graphics unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A processor comprising:
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a plurality of cores of the processor, the plurality of cores including a first core operable at a first voltage and at a first frequency, and a second core operable at a second voltage independent of the first voltage and at a second frequency different from the first frequency; a graphics unit of the processor, the graphics unit operable at a first variable frequency; and an interconnect of the processor to couple the first core, the second core and the graphics unit to a memory external to the processor, the interconnect operable at a second variable frequency, the second variable frequency based at least in part on a value of the first variable frequency. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. An apparatus comprising:
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a plurality of core means, a first core means of the plurality of core means for operating at a first voltage and a second core means of the plurality of core means for operating at a second voltage, the second voltage independent of the first voltage; the first core means of the plurality of core means to be associated with a first frequency and the second core means of the plurality of core means to be associated with a second frequency, wherein the first and second frequencies may be different from each other; a graphics means, wherein a driver means of the graphics means for controlling execution on the graphics means; an interconnect means for coupling the first core means, the second core means and the graphics means to a memory external to the apparatus; and a power control means for controlling a frequency of the interconnect means based at least in part on a frequency of the graphics means, wherein the graphics means is operable at a first plurality of frequencies and the interconnect means is operable at a second plurality of frequencies, and the power control means for updating the frequency of the interconnect means to another one of the second plurality of frequencies based at least in part on the frequency of the graphics means. - View Dependent Claims (19, 20)
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Specification