System and method for partitioning of memory units into non-conflicting sets
First Claim
1. A method for managing memory in a computer comprising:
- using known memory-address constraints to identify at least one input set of potentially conflicting memory addresses; and
for each of the at least one input set of potentially conflicting memory addresses, and iteratively for each of the memory addresses in the at least one input set;
loading a current memory address, belonging to the at least one input set, into a processor cache;
detecting whether an eviction occurs from the processor cache as a result of the loading of the current memory address into the processor cache;
if an eviction is detected;
adding the current memory address to a conflict set of memory addresses;
flushing the processor cache; and
loading the conflict set into the processor cache;
if no eviction is detected, determining whether all of the input set of potentially conflicting memory addresses has been loaded into the processor cache and, if not, loading a next one of the input set of potentially conflicting memory addresses into the processor cache;
whereby the input set of potentially conflicting memory addresses is determined to be partitioned into a plurality of partitions such that memory addresses that conflict in the processor cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict in the processor cache.
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Accused Products
Abstract
A system and method of operation exploit the limited associativity of a single cache set to force observable cache evictions and discover conflicts. Loads are issued to input memory addresses, one at a time, until a cache eviction is detected. After observing a cache eviction on a load from an address, that address is added to a data structure representing the current conflict set. The cache is then flushed, and loads are issued to all addresses in the current conflict set, so that all known conflicting addresses are accessed first, ensuring that the next cache miss will occur on a different conflicting address. The process is repeated, issuing loads from all input memory addresses, incrementally finding conflicting addresses, one by one. Memory addresses that conflict in the cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict.
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Citations
20 Claims
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1. A method for managing memory in a computer comprising:
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using known memory-address constraints to identify at least one input set of potentially conflicting memory addresses; and for each of the at least one input set of potentially conflicting memory addresses, and iteratively for each of the memory addresses in the at least one input set; loading a current memory address, belonging to the at least one input set, into a processor cache; detecting whether an eviction occurs from the processor cache as a result of the loading of the current memory address into the processor cache; if an eviction is detected; adding the current memory address to a conflict set of memory addresses; flushing the processor cache; and loading the conflict set into the processor cache; if no eviction is detected, determining whether all of the input set of potentially conflicting memory addresses has been loaded into the processor cache and, if not, loading a next one of the input set of potentially conflicting memory addresses into the processor cache; whereby the input set of potentially conflicting memory addresses is determined to be partitioned into a plurality of partitions such that memory addresses that conflict in the processor cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict in the processor cache. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system for managing memory in a computer comprising:
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a processor; a processor cache; a cache partitioning module being configured for; using known memory-address constraints to identify at least one input set of potentially conflicting memory addresses; and for each of the at least one input set of potentially conflicting memory addresses, and iteratively for each of the memory addresses in the at least one input set; loading a current memory address, belonging to the at least one input set, into the processor cache; detecting whether an eviction occurs from the processor cache as a result of the loading of the current memory address into the processor cache; if an eviction is detected; adding the current memory address to a conflict set of memory addresses; flushing the processor cache; and loading the conflict set into the processor cache; if no eviction is detected, determining whether all of the input set of potentially conflicting memory addresses has been loaded into the processor cache and, if not, loading a next one of the input set of potentially conflicting memory addresses into the processor cache; whereby the input set of potentially conflicting memory addresses is determined to be partitioned into a plurality of partitions such that memory addresses that conflict in the processor cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict in the processor cache. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A non-transitory computer-readable storage medium storing instructions, the instructions, when executed by a processor, causing the processor to:
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use known memory-address constraints to identify at least one input set of potentially conflicting memory addresses; and for each of the at least one input set of potentially conflicting memory addresses, and iteratively for each of the memory addresses in the at least one input set; load a current memory address, belonging to the at least one input set, into a processor cache; detect whether an eviction occurs from the processor cache as a result of the loading of the current memory address into the processor cache; if an eviction is detected; add the current memory address to a conflict set of memory addresses; flush the processor cache; and load the conflict set into the processor cache; if no eviction is detected, determine whether all of the input set of potentially conflicting memory addresses has been loaded into the processor cache and, if not, load a next one of the input set of potentially conflicting memory addresses into a processor cache; whereby the input set of potentially conflicting memory addresses is determined to be partitioned into a plurality of partitions such that memory addresses that conflict in the processor cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict in the processor cache. - View Dependent Claims (18, 19, 20)
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Specification