Semiconductor memory device capable of shortening erase time
First Claim
1. A semiconductor memory device comprising:
- a memory cell array in which memory cells are provided;
word lines, including a first word line, a second word line and third word lines, connected to the memory cells, and the third word lines located between the first and second word lines; and
a control circuit,wherein the memory cell array has at least two select transistors, the memory cells are connected in series between the select transistors, the select transistors have gates connected to at least two select lines, the first word line is connected to a first memory cell of the memory cells next to at least one of the select transistors, the second word line is connected to a second memory cell of the memory cells next to at least another one of the select transistors, and the third word lines are connected to third memory cells of the memory cells, andwherein the control circuit erases the first, second and third memory cells in an erase operation, the control circuit verifies the third memory cells in an erase verify operation after the erase operation, and the control circuit, in the erase verify operation, sets a first voltage to the first word line, sets a second voltage to the second word line, and sets a third voltage less than the first and second voltages to the third word lines.
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Accused Products
Abstract
In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
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Citations
13 Claims
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1. A semiconductor memory device comprising:
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a memory cell array in which memory cells are provided; word lines, including a first word line, a second word line and third word lines, connected to the memory cells, and the third word lines located between the first and second word lines; and a control circuit, wherein the memory cell array has at least two select transistors, the memory cells are connected in series between the select transistors, the select transistors have gates connected to at least two select lines, the first word line is connected to a first memory cell of the memory cells next to at least one of the select transistors, the second word line is connected to a second memory cell of the memory cells next to at least another one of the select transistors, and the third word lines are connected to third memory cells of the memory cells, and wherein the control circuit erases the first, second and third memory cells in an erase operation, the control circuit verifies the third memory cells in an erase verify operation after the erase operation, and the control circuit, in the erase verify operation, sets a first voltage to the first word line, sets a second voltage to the second word line, and sets a third voltage less than the first and second voltages to the third word lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification