Structure and formation method of fin-like field effect transistor

• US 10,037,921 B2
• Filed: 11/18/2016
• Issued: 07/31/2018
• Est. Priority Date: 06/12/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jangjian, Shiu-Ko, Lin, Tzu-Kai, Jeng, Chi-Cherng
• Primary Examiner(s): Pham, Long
• Application Number:
  US15/355,626
• Publication Number:
  US 20170069545A1
• Time in Patent Office: 620 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of carbon greater than that of the epitaxially grown source/drain structure.

Claims

1. A method for forming a semiconductor device, comprising:

forming a first fin structure over a semiconductor substrate;

forming a second fin structure over the semiconductor substrate;

forming a first gate stack over the semiconductor substrate and covering a portion of the first fin structure;

forming a second gate stack over the semiconductor substrate and covering a portion of the second fin structure;

epitaxially growing first source/drain structures over the first fin structure and adjacent to the first gate stack; and

forming a semiconductor protection layer over the first source/drain structures while the first gate stack is disposed over the portion of the first fin structure, wherein the forming the semiconductor protection layer includes a varying an atomic composition of carbon during the forming the semiconductor protection layer;

blocking the second fin structure before epitaxially growing the first source/drain structures and before forming the semiconductor protection layer are performed;

epitaxially growing second source/drain structures over the second fin structure and adjacent to the second gate stack, wherein the semiconductor protection layer is blocked before the second source/drain structures are grown.

2. The method for forming a semiconductor device as claimed in claim 1, wherein the semiconductor protection layer is epitaxially grown on the first source/drain structures.

3. The method for forming a semiconductor device as claimed in claim 1, wherein the first source/drain structures and the semiconductor protection layer are formed in-situ in a same process chamber.

4. The method for forming a semiconductor device as claimed in claim 1,

wherein the blocking the semiconductor protection layer before the second source/drain structures are grown includes forming a mask layer of a dielectric material over the semiconductor protection layer.

5. The method for forming a semiconductor device as claimed in claim 4, further comprising forming a second semiconductor protection layer over the second source/drain structures after the blocking of the semiconductor protection layer.

6. The method for forming a semiconductor device as claimed in claim 1, wherein the varying the atomic composition of carbon during the forming the semiconductor protection layer includes increasing the atomic composition of carbon during a deposition process.

7. The method for forming a semiconductor device as claimed in claim 1, wherein the epitaxially growing the first source/drain structures includes depositing silicon, and wherein the forming the semiconductor protection layer includes depositing silicon and carbon.

8. The method for forming a semiconductor device as claimed in claim 1, wherein the epitaxially growing the first source/drain structures includes depositing silicon germanium, and wherein the forming the semiconductor protection layer includes depositing silicon, germanium and carbon.

19. The method of claim 1, wherein the epitaxially growing the first source/drain structures is performed after the forming the first gate stack.

20. The method of claim 1, wherein the varying the atomic composition of carbon during the forming the semiconductor protection layer includes increasing the atomic composition of carbon from an interface with one of the first source/drain structures to a top surface of the semiconductor protection layer.

9. A method of fabricating a semiconductor device structure, comprising:

forming a first fin structure and a second fin structure over a semiconductor substrate;

forming a first gate stack over a portion of the first fin structure and a second gate stack over a portion of the second fin structure;

epitaxially growing a first source/drain structure adjacent the first gate stack while masking a portion of the second fin structure;

after growing the first source/drain structure, forming a first protection layer over the first source/drain structure;

epitaxially growing a second source/drain structure adjacent the second gate stack while masking the first source/drain structure and the first protection layer; and

after growing the second source/drain structure, forming a second protection layer over the second source/drain structure.

10. The method of claim 9, wherein the first gate stack is associated with an NMOS device and the second gate stack is associated with a PMOS device.

11. The method of claim 9, wherein the forming the first protection layer includes epitaxially growing the first protection layer on the first source/drain structure;

and wherein the forming the second protection layer includes epitaxially growing the second protection layer on the second source/drain structure.

12. The method of claim 9, wherein at least one of the forming the first protection layer and the forming the second protection layer includes varying an atomic concentration of carbon during deposition.

13. The method of claim 9, wherein the first and second protection layers have a different composition.

14. The method of claim 13, wherein the first protection layer includes silicon and carbon and the second protection layer includes silicon, germanium and carbon.

15. A method for forming a semiconductor device, comprising:

forming a fin structure over a semiconductor substrate;

forming a gate stack over the semiconductor substrate and covering a portion of the fin structure;

after forming the gate stack, epitaxially growing a source/drain structure including silicon and germanium on the fin structure adjacent the gate stack; and

forming a protection layer on the source/drain structure, wherein the protection layer includes carbon, silicon and germanium, wherein the forming the protection layer includes varying an atomic concentration of carbon by increasing the atomic concentration of carbon from an interface with the source/drain structure to a top surface.

16. The method of claim 15, wherein the forming the protection layer is performed in-situ with the epitaxially growing of the source/drain structure.

17. The method of claim 15, wherein the forming the protection layer is performed by one of selective epitaxial growth (SEG) process, a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, an ultra-high vacuum CVD (UHV-CVD) process, a molecular beam epitaxy process, or a combination thereof.

18. The method of claim 17, further comprising:

annealing the semiconductor substrate after epitaxially growing the source/drain structure and before forming the protection layer.