Integrated display system with multi-color light emitting diodes (LEDs)

• US 10,037,981 B2
• Filed: 05/18/2017
• Issued: 07/31/2018
• Est. Priority Date: 05/18/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Banna, Srinivasa, Jha, Sanjay, Nayak, Deepak, Jacob, Ajey P.
• Primary Examiner(s): Smith, Bradley K
• Application Number:
  US15/599,465
• Publication Number:
  US 20170358562A1
• Time in Patent Office: 439 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/08147 the bonding area connecting to a bonding area disposed in a recess of the surface of the body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals of the LEDs. The backplane (BP) device comprises a BP substrate having top and bottom surfaces. A plurality of system on chip (SoC) chips are bonded to chip pads disposed on a bottom surface of the BP device. The SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.

Claims

1. A display system comprising:

a light emitting diode (LED) device, wherein the LED device comprises

a plurality of LEDs having LED terminals, and

an LED bonding surface comprising a dielectric layer with LED bonding surface contact pads coupled to diode terminals of the LEDs;

a backplane (BP) device, the BP device comprises a BP substrate having top and bottom surfaces, wherein the top surface comprises

complementary metal oxide semiconductor (CMOS) components,

a back-end-of-line (BEOL) dielectric having a plurality interlevel dielectric (ILD) layers, wherein an ILD layer includes a contact level with contacts and a metal level with metal lines, the ILD layer provides interconnections for the CMOS components,

a top level of the BEOL dielectric with BP bonding surface contact pads, wherein the BP bonding surface is bonded to the LED bonding surface, the LED bonding surface contact pads and the BP bonding surface contact pads provides interconnections between the BP and LED devices,

a plurality of BP through silicon via (TSV) contacts disposed in the BP substrate, wherein the BP TSV contacts are interconnected to TSV contact regions on the BEOL dielectric, and

a redistribution layer (RDL) having top and bottom RDL surfaces, the top RDL surface is disposed on the bottom surface of the BP substrate, wherein the redistribution layer provides interconnection to the BP TSV contacts and chip pads disposed on the bottom RDL surface; and

a plurality of system on chip (SoC) chips bonded to the chip pads on the bottom RDL surface, wherein the SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.

2. The display system of claim 1 wherein the LEDs of the LED device comprise multi-quantum well (MQW) LEDs.

3. The display system of claim 1 wherein the SoC chips comprise chips of the display system which include CPU cores, DSP cores, on-chip memories, audio/video codes, eye/head tracking sensors, wireless interconnections, or a combination thereof.

4. A display system comprising:

an LED device, wherein the LED device comprises an LED bonding surface with LED contact pads coupled to terminals of LEDs of the LED device;

a backplane (BP) device, the BP device comprises a BP substrate having top and bottom surfaces, wherein the top surface comprises

complementary metal oxide semiconductor (CMOS) components and a back-end-of-line (BEOL) dielectric with a plurality of interlevel dielectric (ILD) layers with interconnections, a top surface of the BEOL dielectric includes BEOL contact pads and serves as a BP bonding surface,

wherein the BP bonding surface and LED bonding surface are bonded together to result in a common bonded surface for the bonded BP and LED devices, wherein the BEOL contacts and LED contacts are coupled to provide interconnections between the CMOS components of the BP device and LEDs of the LED device, and

a plurality of BP through silicon via (TSV) contacts disposed in the BP substrate, wherein the BP TSV contacts are interconnected to TSV contact regions on the BEOL dielectric;

a redistribution layer (RDL) having top and bottom RDL surfaces, the top RDL surface is disposed on the bottom surface of the BP substrate, wherein the redistribution layer provides interconnection to the BP TSV contacts and chip pads disposed on the bottom RDL surface; and

a plurality of system on chip (SoC) chips bonded to the chip pads on the bottom RDL surface, wherein the SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.

5. The display system of claim 4 wherein the common bonded surface comprises a fusion bonded surface.

6. The display system of claim 4 wherein the SoC chips comprise chips of the display system.

7. The display system of claim 6 wherein the SoC chips comprise CPU cores, DSP cores, on-chip memories, audio/video codes, eye/head tracking sensors, wireless interconnections, or a combination thereof.

8. The display system of claim 4 wherein the LEDs of the LED device comprise multi-quantum well (MQW) LEDs.

9. The display system of claim 4 wherein the LED device is configured as an inverted LED device, the inverted LED device comprises:

a dielectric layer covering the LEDs of the LED device, the dielectric layer serves as the bonding surface of the inverted LED device;

each LED of the LED device comprises an LED base, wherein LED bases of the LEDs of the LED device serve as first LED terminals, the first LED terminals are commonly coupled to form a common first LED terminal of the LEDs; and

each LED of the LED device includes a second terminal, wherein the second terminal is a non-common terminal of the LEDs of the LED device.

10. The display system of claim 9 wherein a transparent conductive electrode is disposed over the bases of the LEDs and serve as the common LED terminal.

11. The display system of claim 9 wherein:

a conductive base layer is disposed over the bases of the LEDs; and

a transparent conductive electrode is disposed on the conductive base layer, the transparent conductive electrode serves as the common LED terminal.

12. The display system of claim 9 wherein the LED contact pads are coupled to the common and non-common terminals of the LEDs.

13. The display system of claim 4 wherein the LED device is configured as a non-inverted LED device, the non-inverted LED device comprises:

an LED substrate on which LEDs of the LED device are disposed on a first major LED substrate surface;

LED wells in the substrate, the LED wells are coupled to first LED terminals of the LEDs;

first LED TSV contacts coupled to the LED wells, second LED TSV contacts for coupling to second LED terminals of the LEDs, wherein the second LED terminals of the LEDs are commonly coupled to serve as a common second LED terminal; and

a dielectric layer disposed on a second major LED substrate surface, the dielectric layer includes the LED contact pads coupled to the first and second LED TSV contacts, wherein the dielectric layer serves as the LED bonding surface.

14. The display system of claim 13 wherein a transparent conductive electrode is disposed over the LEDs and serve as the common second LED terminal.

15. The display system of claim 14 wherein the transparent conductive electrode contacts the second LED terminals of the LEDs.

16. A system comprising:

a light emitting diode (LED) device having a plurality of LEDs with LED terminals, the LED device includes a dielectric layer having a top surface which includes LED contact pads coupled to the LED terminal, the dielectric layer serves as an LED bonding surface;

a backplane (BP) device having with complementary metal oxide semiconductor (CMOS) components disposed on a first surface of a BP substrate, the BP device includes a back-end-of-line (BEOL) dielectric with interconnections, the BEOL dielectric includes a top surface with BP contact pads and serves as a BP bonding surface,

a common bonded surface of the BP and LED devices resulting from bonding the BP and LED bonding surfaces, wherein the BP contact pads and LED contact pads are coupled to interconnect the CMOS components of the BP device to LEDs of the LED device;

a plurality of BP contacts disposed in the BP substrate, wherein the BP contacts are interconnected to contact regions on the BEOL dielectric; and

a redistribution layer (RDL) having top and bottom RDL surfaces, the top RDL surface is disposed on a second surface of the BP substrate, wherein the RDL interconnects the BP contacts and chip pads disposed on the bottom RDL surface.

17. The system of claim 16 comprises a plurality of system on chip (SoC) chips bonded to the chip pads on the bottom RDL surface, wherein the SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.

18. The system of claim 16 wherein the LEDs of the LED device comprise multi-quantum well (MQW) LEDs.

19. The system of claim 16 wherein the LED device is configured as a non-inverted LED device, the non-inverted LED device comprises:

an LED substrate on which LEDs of the LED device are disposed on a first major LED substrate surface;

LED wells in the substrate, the LED wells are coupled to first LED terminals of the LEDs;

first LED contacts coupled to the LED wells, second LED contacts for coupling to second LED terminals of the LEDs, wherein the second LED terminals of the LEDs are commonly coupled to serve as a common second LED terminal; and

a dielectric layer disposed on a second major LED substrate surface, the dielectric layer includes the LED contact pads coupled to the first and second LED contacts, wherein the dielectric layer serves as the LED bonding surface.

20. The system of claim 16 wherein the LED device is configured as an inverted LED device, the inverted LED device comprises:

a dielectric layer covering the LEDs of the LED device, the dielectric layer serves as the bonding surface of the inverted LED device;

each LED of the LED device comprises an LED base, wherein LED bases of the LEDs of the LED device serve as first LED terminals, the first LED terminals are commonly coupled to form a common first LED terminal of the LEDs; and

each LED of the LED device includes a second terminal, wherein the second terminal is a non-common terminal of the LEDs of the LED device.