Semiconductor device and a method for fabricating the same

• US 10,037,995 B2
• Filed: 11/18/2016
• Issued: 07/31/2018
• Est. Priority Date: 02/10/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liao, Shun-Jang, Liao, Chia-Chun, Wang, Shu-Hui, Chang, Shih-Hsun
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Kim, Tong-Ho
• Application Number:
  US15/355,717
• Publication Number:
  US 20170229461A1
• Time in Patent Office: 620 Days
• Field of Search: 257369, 438275, 438592
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

Claims

1. A method of manufacturing gate structures for plural field effect transistors (FETs) in a semiconductor device, the method comprising:

forming a gate dielectric layer over each of channel layers for the FETs;

forming a first conductive layer over the gate dielectric layer;

forming a work function adjustment material (WFM) layer over the first conductive layer; and

forming a second conductive layer over the WFM layer, wherein;

the forming the WFM layer for at least one FET includes at least one first operation of forming one or more conductive layers and etching the one or more conductive layers, thereby exposing the first conductive layer,

the forming the WFM layer for at least one FET includes at least one second operation of forming a conductive layer and not etching the conductive layer,

the FETs include a first n-channel FET, a second n-channel FET and a third n-channel FET,

the forming the WFM layer for the first n-channel FET includes three first operations, and

the forming the WFM layer for the second and third n-channel FETs includes two first operations.

2. The method of claim 1, wherein:

the FETs further include a first p-channel FET, a second p-channel FET and a third p-channel FET,

the forming the WFM layer for the first and second p-channel FET includes one first operation, and

the forming the WFM layer for the second and third p-channel FETs includes no first operation.

3. A method of manufacturing gate electrode structures for plural field effect transistors (FETs) including a first n-channel FET, a second n-channel FET and a third n-channel FET, which have different threshold voltages from each other, the method comprising:

forming a gate dielectric layer over each of channel layers for the first to third n-channel FETs;

forming a first conductive layer over the gate dielectric layer for the first to third n-channel FETs; and

forming one or more work function adjustment material (WFM) layers over the first conductive layer for the first to third n-channel FETs, wherein;

a first WFM layer of the first n-channel FET includes a layer of a first conductive material,

a second WFM layer of the second n-channel FET includes a layer of a second conductive material and a layer of the first conductive material disposed on the layer of the second conductive material,

a third WFM layer of the third n-channel FET includes a layer of the second conductive material and a layer of the first conductive material disposed on the layer of the second conductive material,

the first WFM layer is formed after performing three first operations of forming one or more conductive layers and etching the one or more conductive layers, thereby exposing the first conductive layer.

4. The method of claim 3, wherein a thickness of the layer of the second conductive material of the third WFM layer is greater than a thickness of the layer of the second conductive material of the second WFM layer.

5. The method of claim 4, wherein the first conductive material is TiAlC and the second conductive material is TiN.

6. The method of claim 4, wherein the first conductive layer is TaN.

7. The method of claim 3, wherein the second WFM layer is formed after performing two first operations of forming one or more conductive layers and etching the one or more conductive layers, thereby exposing the first conductive layer.

8. The method of claim 3, wherein:

the third WFM layer is formed after performing two first operation of forming one or more conductive layers and etching the one or more conductive layers, thereby exposing the first conductive layer,

one of the two first operations for the second WFM layer is performed at a same time as one of the two first operations for the third WFM layre, and

another of the two first operations for the second WFM layer is performed at a different timing than another of the two first operations for the third WFM layer.

9. The method of claim 3, wherein the first to third WFM layers are formed sequentially by:

forming a first layer on the first conductive layer on the first conductive layer for the first to third n-channel FET, respectively;

removing the first layer for the third n-channel FET, thereby exposing the first conductive layer;

forming a second layer on the first layer for the first and second n-channel FETs and on the exposed first conductive layer for the third n-channel FET;

removing the first and second layers for the first and second n-channel FETs, thereby exposing the first conductive layer;

forming a third layer on the exposed first conductive layer for the first and second n-channel FETs, and on the second layer for the third n-channel FET;

removing the third layer for the first n-channel FET, thereby exposing the first conductive layer; and

forming a fourth layer on the exposed first conductive layer for the first n-channel FET, and on the third layer for the second and third n-channel FETs.

10. A method of manufacturing gate electrode structures for plural field effect transistors (FETs) including a first p-channel FET, a second p-channel FET and a third p-channel FET, which have different threshold voltages from each other, the method comprising:

forming a gate dielectric layer over each of channel layers for the first to third p-channel FETs;

forming a first conductive layer over the gate dielectric layer for the first to third p-channel FETs; and

forming one or more work function adjustment material (WFM) layers over the first conductive layer for the first to third p-channel FETs, wherein;

forming a first WFM layer of the first p-channel FET includes performing one operation of forming one or more conductive layers and etching the one or more conductive layers, thereby exposing the first conductive layer,

forming a second WFM layer of the second p-channel FET includes by performing one operation of forming one or more conductive layers and etching the one or more conductive layers, thereby exposing the first conductive layer, and

forming a third WFM layer of the third p-channel FET includes no operation of forming one or more conductive layers and etching the one or more conductive layers, thereby exposing the first conductive layer,

wherein the first WFM layer is formed by forming a conductive material layer three times.

11. The method of claim 10, wherein a thickness of the layer of the first WFM layer is smaller than a thickness of the second WFM layer and the thickness of the second WFM layer is smaller than a thickness of the third WFM layer.

12. The method of claim 10, wherein:

the first to third WFM layers include TiN, and TiAlC.

13. The method of claim 10, wherein the first conductive layer is TaN.

14. The method of claim 10, wherein the second WFM layer is by forming a conductive material layer four times.

15. The method of claim 14, wherein the second WFM layer is by forming a conductive material layer five times.

16. The method of claim 10, wherein:

the one operation for the second WFM layer is performed at a different timing than the one operation for the first WFM layer.