Single-poly nonvolatile memory cell structure having an erase device

• US 10,038,003 B2
• Filed: 12/20/2016
• Issued: 07/31/2018
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Sun, Wein-Town, Chen, Wei-Ren, Chen, Ying-Je
• Primary Examiner(s): Vu, David
• Application Number:
  US15/384,323
• Publication Number:
  US 20170207230A1
• Time in Patent Office: 588 Days
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell

Abstract

A single-poly nonvolatile memory cell includes an SOI substrate having a semiconductor layer, a first OD region and a second OD region on the semiconductor layer, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor disposed on the first OD region. The PMOS floating gate transistor is serially connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension is continuously extended from the floating gate to the second OD region and is capacitively coupled to the second OD region.

Claims

1. A single-poly nonvolatile memory cell, comprising:

a silicon-on-insulator (SOI) substrate comprising a silicon substrate, a buried oxide layer, and a semiconductor layer;

a first oxide define (OD) region and a second oxide define (OD) region on the semiconductor layer;

an isolation region in the semiconductor layer, the isolation region separating the first OD region from the second OD region;

a PMOS select transistor disposed on the first OD region;

a PMOS floating gate transistor disposed on the first OD region, the PMOS floating gate transistor being serially connected to the PMOS select transistor, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region;

a floating gate extension continuously extended from the floating gate to the second OD region and being capacitively coupled to the second OD region, wherein an overlapping area between the floating gate extension and the second OD region is smaller than an overlapping area between the floating gate and the first OD region;

a third oxide define (OD) region disposed on a side of the first OD region opposite to the second OD region;

an N well in the semiconductor layer, wherein the N well completely overlaps with the first OD region and the third OD region; and

a charge collecting region disposed in the third OD region and being contiguous with the first OD region, wherein the third OD region and the charge collecting region are situated within the N well.

2. The single-poly nonvolatile memory cell according to claim 1, wherein the PMOS select transistor comprises a select gate, a select gate oxide layer between the select gate and the semiconductor layer, a P⁺ source doping region, and a P⁺ drain/source doping region, wherein the P⁺ source doping region is electrically connected to a source line.

3. The single-poly nonvolatile memory cell according to claim 2, wherein the PMOS floating gate transistor comprises a floating gate, a floating gate oxide layer between the floating gate and the semiconductor layer, a P⁺ drain doping region and the P⁺ drain/source doping region, wherein the P⁺ drain/source doping region is shared by the PMOS select transistor and the PMOS floating gate transistor.

4. The single-poly nonvolatile memory cell according to claim 1 further comprising:

an ion well in the semiconductor layer and completely overlapping with the second OD region; and

a heavily doped region in the ion well within the second OD region.

5. The single-poly nonvolatile memory cell according to claim 4, wherein the ion well comprises N well or P well.

6. The single-poly nonvolatile memory cell according to claim 4, wherein the heavily doped region is an N⁺ doping region.

7. The single-poly nonvolatile memory cell according to claim 4, wherein the heavily doped region is a P⁺ doping region.

8. The single-poly nonvolatile memory cell according to claim 4, wherein the floating gate extension traverses the isolation region between the first OD region and the second OD region and partially overlaps with the second OD region to capacitively couple to the heavily doped region.

9. The single-poly nonvolatile memory cell according to claim 4, wherein the second OD region, the heavily doped region, the floating gate oxide layer, and the floating gate extension that is capacitively coupled to the heavily doped region together constitute an erase device.

10. The single-poly nonvolatile memory cell according to claim 4, wherein in operation, the select gate is coupled to a select gate voltage V_SG, the P⁺ source doping region of the PMOS select transistor is electrically coupled to a source line voltage V_SL, the P⁺ drain/source doping region and the floating gate are electrically floating, the P⁺ drain doping region of the PMOS floating gate transistor is electrically coupled to a bit line voltage V_BL, and the heavily doped region is electrically coupled to an erase line voltage V_EL.

11. The single-poly nonvolatile memory cell according to claim 1, wherein the charge collecting region comprises an N⁺ doping region in the third OD region, a bridge region connecting the N⁺ doping region with the semiconductor layer directly under the floating gate.

12. The single-poly nonvolatile memory cell according to claim 11, wherein the N well overlaps with the third OD region and the bridge region.

13. The single-poly nonvolatile memory cell according to claim 1 further comprising:

an N⁺ doping region that is contiguous with the P⁺ doping region on the same side of the select gate, thereby forming a butted contact region.