Via support structure under pad areas for BSI bondability improvement

• US 10,038,025 B2
• Filed: 12/15/2016
• Issued: 07/31/2018
• Est. Priority Date: 12/29/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Sin-Yao, Wang, Ching-Chun, Yaung, Dun-Nian, Hung, Feng-Chi
• Primary Examiner(s): Le, Thao P
• Application Number:
  US15/380,186
• Publication Number:
  US 20170186802A1
• Time in Patent Office: 593 Days
• Field of Search: None
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

Some embodiments of the present disclosure relate to an integrated chip having a via support structure underlying a bond pad. The integrated chip has an image sensing element arranged within a substrate. A bond pad region extends through the substrate, at a location laterally offset from the image sensing element, to a first metal interconnect wire arranged within a dielectric structure along a front-side of the substrate. A bond pad is arranged within the bond pad region and contacts the first metal interconnect wire. A via support structure is arranged within the dielectric structure and has one or more vias that are separated from the bond pad by the first metal interconnect wire. One or more additional vias are arranged within the dielectric structure at a location laterally offset from the bond pad region. The one or more vias have larger sizes than the one or more additional vias.

Claims

1. An integrated chip, comprising:

an image sensing element arranged within a semiconductor substrate, wherein the semiconductor substrate comprises sidewalls defining a bond pad opening extending through the semiconductor substrate, wherein the bond pad opening extends from a back-side of the semiconductor substrate to a first metal interconnect wire arranged within a dielectric structure located along a front-side of the semiconductor substrate;

a conductive bond pad arranged within the bond pad opening and contacting the first metal interconnect wire;

a via support structure arranged within the dielectric structure and comprising one or more vias separated from the conductive bond pad by the first metal interconnect wire; and

one or more additional vias arranged within the dielectric structure at a location laterally offset from the bond pad opening, wherein the one or more vias have larger sizes than the one or more additional vias.

2. The integrated chip of claim 1, wherein the one or more vias and the one or more additional vias have lower surfaces facing the substrate, which are substantially co-planar.

3. The integrated chip of claim 1,

wherein the one or more vias respectively have a first size that is greater than approximately 130% a second size of respective ones of the one or more additional vias;

and

wherein the first size is configured to provide for a pattern density that mitigates damage caused by a force of a bonding process on the conductive bond pad.

4. The integrated chip of claim 1, wherein the one or more vias respectively have a width having a first size and are separated by a space having a second size that is less than the width.

5. The integrated chip of claim 1, wherein the via support structure has a metal pattern density that is greater than or equal to approximately 19%.

6. The integrated chip of claim 1, wherein the via support structure has a metal pattern density that is greater than or equal to approximately 40%.

7. The integrated chip of claim 1,

wherein the one or more vias have a length extending in a first direction and a width extending in a second direction that is perpendicular to the first direction;

and

wherein the length is larger than the width.

8. The integrated chip of claim 7, wherein the length is more than twice as large as the width.

9. The integrated chip of claim 1, wherein the one or more vias respectively comprise sidewalls continuously surrounding one or more openings extending through a via.

10. The integrated chip of claim 1, further comprising:

a via array comprising a first plurality of vias arranged below the via support structure; and

a second plurality of vias arranged at a second location laterally offset from the bond pad opening, wherein the second plurality of vias have a same size as the first plurality of vias.

11. The integrated chip of claim 1, further comprising:

a plurality of conductive contacts arranged within a first ILD layer disposed between the first metal interconnect wire and the semiconductor substrate, wherein the bond pad opening extends through the first ILD layer.

12. An integrated chip, comprising:

a substrate;

a bond pad arranged within a bond pad region extending through the substrate, wherein the bond pad region extends from a back-side of the substrate to a first metal interconnect wire arranged within a dielectric structure located along a front-side of the substrate; and

a via support structure comprising one or more vias arranged within the dielectric structure at a location separated from the substrate by the first metal interconnect wire, wherein the via support structure has a metal pattern density that is greater than or equal to approximately 40% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.

13. The integrated chip of claim 12, wherein the one or more vias respectively have a width and are separated by a space that is smaller than the width.

14. The integrated chip of claim 12,

wherein the one or more vias have a length extending in a first direction and a width extending in a second direction that is perpendicular to the first direction;

and

wherein the length is larger than the width.

15. The integrated chip of claim 12, wherein the one or more vias comprise a first via having sidewalls continuously surrounding one or more openings extending through the first via.

16. The integrated chip of claim 12, further comprising:

one or more additional vias having lower surfaces facing the substrate, which are substantially co-planar with lower surfaces of the one or more vias facing the substrate, wherein the one or more additional vias are smaller than the one or more vias.

17. An integrated chip, comprising:

a substrate having interior sidewalls defining an opening extending from a front-side of the substrate to a back-side of the substrate;

a dielectric structure disposed along the front-side of the substrate;

a bond pad extending from between the interior sidewalls to a first interconnect layer surrounded by the dielectric structure;

a plurality of support vias between the first interconnect layer and a second interconnect layer surrounded by the dielectric structure; and

one or more additional vias surrounded by the dielectric structure and having a smaller width than the plurality of support vias, wherein a horizontal plane parallel to the front-side of the substrate extends through the plurality of support vias and the one or more additional vias, and wherein the plurality of support vias extend from under the bond pad to laterally outside of the bond pad.

18. The integrated chip of claim 17, wherein the plurality of support vias are confined between interconnect layers intersecting a vertical projection of the bond pad.

19. The integrated chip of claim 17, wherein the first interconnect layer has a first surface contacting the bond pad and an opposing, second surface contacting the plurality of support vias.

20. The integrated chip of claim 17, wherein the plurality of support vias have heights that are substantially equal to heights of the one or more additional vias.