Via support structure under pad areas for BSI bondability improvement
First Claim
1. An integrated chip, comprising:
- an image sensing element arranged within a semiconductor substrate, wherein the semiconductor substrate comprises sidewalls defining a bond pad opening extending through the semiconductor substrate, wherein the bond pad opening extends from a back-side of the semiconductor substrate to a first metal interconnect wire arranged within a dielectric structure located along a front-side of the semiconductor substrate;
a conductive bond pad arranged within the bond pad opening and contacting the first metal interconnect wire;
a via support structure arranged within the dielectric structure and comprising one or more vias separated from the conductive bond pad by the first metal interconnect wire; and
one or more additional vias arranged within the dielectric structure at a location laterally offset from the bond pad opening, wherein the one or more vias have larger sizes than the one or more additional vias.
1 Assignment
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Accused Products
Abstract
Some embodiments of the present disclosure relate to an integrated chip having a via support structure underlying a bond pad. The integrated chip has an image sensing element arranged within a substrate. A bond pad region extends through the substrate, at a location laterally offset from the image sensing element, to a first metal interconnect wire arranged within a dielectric structure along a front-side of the substrate. A bond pad is arranged within the bond pad region and contacts the first metal interconnect wire. A via support structure is arranged within the dielectric structure and has one or more vias that are separated from the bond pad by the first metal interconnect wire. One or more additional vias are arranged within the dielectric structure at a location laterally offset from the bond pad region. The one or more vias have larger sizes than the one or more additional vias.
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Citations
20 Claims
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1. An integrated chip, comprising:
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an image sensing element arranged within a semiconductor substrate, wherein the semiconductor substrate comprises sidewalls defining a bond pad opening extending through the semiconductor substrate, wherein the bond pad opening extends from a back-side of the semiconductor substrate to a first metal interconnect wire arranged within a dielectric structure located along a front-side of the semiconductor substrate; a conductive bond pad arranged within the bond pad opening and contacting the first metal interconnect wire; a via support structure arranged within the dielectric structure and comprising one or more vias separated from the conductive bond pad by the first metal interconnect wire; and one or more additional vias arranged within the dielectric structure at a location laterally offset from the bond pad opening, wherein the one or more vias have larger sizes than the one or more additional vias. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated chip, comprising:
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a substrate; a bond pad arranged within a bond pad region extending through the substrate, wherein the bond pad region extends from a back-side of the substrate to a first metal interconnect wire arranged within a dielectric structure located along a front-side of the substrate; and a via support structure comprising one or more vias arranged within the dielectric structure at a location separated from the substrate by the first metal interconnect wire, wherein the via support structure has a metal pattern density that is greater than or equal to approximately 40% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad. - View Dependent Claims (13, 14, 15, 16)
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17. An integrated chip, comprising:
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a substrate having interior sidewalls defining an opening extending from a front-side of the substrate to a back-side of the substrate; a dielectric structure disposed along the front-side of the substrate; a bond pad extending from between the interior sidewalls to a first interconnect layer surrounded by the dielectric structure; a plurality of support vias between the first interconnect layer and a second interconnect layer surrounded by the dielectric structure; and one or more additional vias surrounded by the dielectric structure and having a smaller width than the plurality of support vias, wherein a horizontal plane parallel to the front-side of the substrate extends through the plurality of support vias and the one or more additional vias, and wherein the plurality of support vias extend from under the bond pad to laterally outside of the bond pad. - View Dependent Claims (18, 19, 20)
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Specification