Threshold adjustment for quantum dot array devices with metal source and drain

• US 10,038,072 B2
• Filed: 12/29/2015
• Issued: 07/31/2018
• Est. Priority Date: 09/25/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John H.
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): Yemelyanov, Dmitriy
• Application Number:
  US14/982,316
• Publication Number:
  US 20160111521A1
• Time in Patent Office: 945 Days
• Field of Search: 438212, 438272
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase V_t. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease V_t. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies V_t. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Claims

1. A method of making a transistor, the method comprising:

forming two isolation trenches in a substrate;

forming source and drain regions by doping portions of the substrate between the two isolation trenches;

forming a first recessed area between the source and drain regions by removing doped portions of the substrate;

forming a second recessed area in the source region by removing doped portions of the substrate;

forming a channel in the first recessed area of the substrate;

forming a metal gate in the first recessed area of the substrate;

forming a silicide layer on bottom and side walls of the second recessed area;

selecting a threshold voltage for the transistor; and

embedding a first metal quantum dot into the silicide layer in the source region, the first metal quantum dot having a selected molecular composition that sets a threshold voltage of the transistor to the selected threshold voltage.

2. The method of claim 1, further comprising:

forming a third recessed area in the drain region by removing doped portions of the substrate;

forming the silicide layer on bottom and side walls of the third recessed area; and

embedding a second metal quantum dot into the silicide layer in the drain region, the second metal quantum dot having a selected composition that, together with the selected molecular composition of the first metal quantum dot in the source region, sets the threshold voltage of the transistor to the selected threshold voltage.

3. The method of claim 1 wherein embedding the first metal quantum dot uses an atomic layer deposition technique.

4. The method of claim 1 wherein the metal gate includes a top surface and a bottom surface opposite the top surface, the bottom surface being closer to the channel than the top surface, the top surface of the metal gate being coplanar with a top surface of the substrate.

5. The method of claim 1 wherein doping portions of the substrate includes implanting ions into the substrate.

6. The method of claim 1 wherein the doping includes incorporating dopants in-situ while depositing an epitaxial layer onto the substrate.

7. The method of claim 1 wherein the embedding further comprises varying the composition of the first metal quantum dot using a mass spectrometer.

8. The method of claim 1 wherein removing the doped portions entails use of an etching process targeted according to a measured doping profile.

9. A method, comprising:

selecting a first threshold voltage;

forming a plurality of n-type field effect transistors in a silicon substrate, the n-type transistors having n-doped source and drain regions that each contain embedded silver bromide quantum dots;

forming a silicide layer lining between each of the embedded silver bromide quantum dots and the respective n-doped source and drain regions on bottom and side walls of the embedded silver bromide quantum dots, the embedded silver bromide quantum dots in the n-type field effect transistors having a molecular composition that causes the plurality of n-type field effect transistors to each have a threshold voltage matched with the selected first threshold voltage;

selecting a second threshold voltage;

forming a plurality of p-type field effect transistors in the silicon substrate, the p-type transistors having p-doped source and drain regions that contain embedded silver bromide quantum dots; and

forming a silicide layer lining between each of the embedded silver bromide quantum dots and the respective p-doped source and drain regions on bottom and side walls of the embedded silver bromide quantum dots, the embedded silver bromide quantum dots in the p-type field effect transistors having a molecular composition that causes the plurality of p-type field effect transistors to have a threshold voltage matched with the selected second threshold voltage.

10. The method of claim 9 wherein the embedded silver bromide quantum dots include neutral clusters of monomers.

11. The method of claim 10 wherein a selected size of the neutral clusters of monomers corresponds to the first and second threshold voltages.

12. The method of claim 9 wherein forming the transistor further includes forming a metal gate having a work function material that includes titanium.

13. A method, comprising:

forming in a silicon substrate a transistor having a doped source with a first recess, a doped drain with a second recess, a channel, and a recessed metal gate;

forming a silicide layer on bottom and side walls of the first recess and the second recess;

selecting a threshold voltage for the transistor; and

forming a first metal quantum dot in the silicide layer at the doped source and a second metal quantum dot in the silicide layer at the doped drain, each of the metal quantum dots having a selected molecular composition of a cluster of monomers that tunes the threshold voltage of the transistor to the selected threshold voltage.

14. The method of claim 13 wherein the selected molecular composition includes silver bromide (AgBr) clusters.

15. The method of claim 14 wherein the silver bromide clusters are rich in silver and the threshold voltage of the transistor is lowered as the metal quantum dots are formed.

16. The method of claim 14 wherein the silver bromide clusters are rich in bromine and the threshold voltage is raised as the metal quantum dots are formed.

17. The method of claim 14 wherein one or more of the doped source, doped drain, and channel are epitaxially grown.

18. The method of claim 17 wherein the source and drain are doped in-situ during the epitaxial growth.

19. The method of claim 13 wherein the source and drain are doped using an ion implantation process.

20. The method of claim 13, further comprising forming a raised source and a raised drain.