3D integrated circuit device

• US 10,038,073 B1
• Filed: 03/10/2018
• Issued: 07/31/2018
• Est. Priority Date: 04/09/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/917,629
• Publication Number:
  US 20180204930A1
• Time in Patent Office: 143 Days
• Field of Search: 257369, 257499
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/0673 : oriented parallel to a substrate
• CPC Class Codes: H01L 29/1066 : Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66272 : Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66704 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66901 : with a PN homojunction gate
• CPC Class Codes: H01L 29/732 : Vertical transistors
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/808 : with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/011 : Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A 3D integrated circuit device, the device including: a first level including a single crystal wafer, the first level includes a plurality of first transistors; a second level overlaying the first level, the second level includes a plurality of second transistors; a third level overlaying the second level, the third level includes a plurality of third transistors; a first metal layer interconnecting the plurality of first transistors; a second metal layer overlaying the third level, where the second level has a first coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first metal layer, where the connection path includes at least one through-layer via, where the through-layer via includes a material, the material has a second co-efficient of thermal expansion, and where the second co-efficient of thermal expansion is within 50 percent of the first coefficient of thermal expansion.

Claims

1. A 3D integrated circuit device, the device comprising:

a first level comprising a single crystal wafer, said first level comprises a plurality of first transistors;

a second level overlaying said first level, said second level comprises a plurality of second transistors;

a third level overlaying said second level, said third level comprises a plurality of third transistors;

a first metal layer interconnecting said plurality of first transistors;

a second metal layer overlaying said third level,

wherein said second level has a first coefficient of thermal expansion; and

a connection path connecting at least one of said plurality of second transistors to said first metal layer,

wherein said connection path comprises at least one through-layer via,

wherein said through-layer via comprises a material, said material has a second co-efficient of thermal expansion,

wherein said second co-efficient of thermal expansion is within 50 percent of said first coefficient of thermal expansion,

wherein at least one of said plurality of first transistors, at least one of said plurality of second transistors and at least one of said plurality of third transistors are aligned to each other with less than 100 nm misalignment,

wherein at least one of said second transistors is at least partially overlaying at least one of said first transistors,

wherein supply of ground or power to at least one of said second transistors is controlled by at least one of said first transistors,

wherein at least one of said second transistors is self-aligned to at least one of said third transistors, and

wherein at least one of said second transistors is a junction-less transistor.

2. The device according to claim 1, further comprising:

a third memory cell comprising at least one of said plurality of third transistors;

a second memory cell comprising at least one of said plurality of second transistors; and

a memory periphery circuit comprising at least one of said plurality of first transistors,

wherein said memory periphery circuit controls said third memory cell and second memory cell.

3. The device according to claim 1,

wherein at least one of said plurality of second transistors is connected to at least one of said plurality of third transistors with an ohmic connection.

4. The device according to claim 1,

wherein said at least one through-layer vias is formed through and in direct contact with a source or drain of at least one of said plurality of second transistors.

5. The device according to claim 1,

wherein said plurality of second transistors comprise a second gate dielectric;

wherein said plurality of third transistors comprise a third gate dielectric, and

wherein said second gate dielectric and said third gate dielectric are part of the same layer.

6. The device according to claim 1,

wherein at least one of said plurality of third transistors is controlled by a third control line,

wherein at least one of said plurality of second transistors is controlled by a second control line, and

wherein a control circuit controlling said second control line and third control line comprises a portion of said plurality of first transistors.

7. The device according to claim 1,

wherein at least one of said plurality of third transistors comprises polysilicon.

8. A 3D integrated circuit device, the device comprising:

a first level comprising a single crystal wafer, said first level comprises a plurality of first transistors;

a second level overlaying said first level, said second level comprises a plurality of second transistors;

a third level overlaying said second level, said third level comprises a plurality of third transistors;

a first metal layer interconnecting said plurality of said first transistors;

a second metal layer overlaying said third level,

wherein said second level has a first coefficient of thermal expansion; and

a connection path connecting at least one of said plurality of second transistors to said first metal layer,

wherein said connection path comprises at least one through-layer via,

wherein said through-layer via comprises a material, said material has a second co-efficient of thermal expansion,

wherein said second co-efficient of thermal expansion is within 50 percent of said first coefficient of thermal expansion,

wherein at least one of said plurality of first transistors, at least one of said plurality of second transistors and at least one of said plurality of third transistors are aligned to each other with less than 100 nm misalignment,

wherein at least one of said plurality of second transistors is at least partially overlaying at least one of said plurality of first transistors,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, and

wherein at least one of said plurality of second transistors is a junction-less transistor.

9. The device according to claim 8, further comprising:

a third memory cell comprising at least one of said plurality of third transistors;

a second memory cell comprising at least one of said plurality of second transistors; and

a memory periphery circuit comprising at least one of said plurality of first transistors,

wherein said memory periphery circuit controls said third memory cell and second memory cell.

10. The device according to claim 8,

wherein at least one of said plurality of second transistors is connected to at least one of said plurality of third transistors with an ohmic connection.

11. The device according to claim 8,

wherein said at least one through-layer via is formed through and in direct contact with a source or drain of at least one of said plurality of second transistors.

12. The device according to claim 8,

wherein said plurality of second transistors comprise a second gate dielectric;

wherein said plurality of third transistors comprise a third gate dielectric, and

wherein said second gate dielectric and said third gate dielectric are part of the same layer.

13. The device according to claim 8,

wherein at least one of said plurality of third transistors is controlled by a third control line,

wherein at least one of said plurality of second transistors is controlled by a second control line, and

wherein a control circuit controlling said second control line and third control line comprises a portion of said plurality of first transistors.

14. The device according to claim 8,

wherein supply of ground or power to at least one of said plurality of second transistors is controlled by at least one of said plurality of first transistors.

15. A 3D integrated circuit device, the device comprising:

a first level comprising a single crystal wafer, said first level comprises a plurality of first transistors;

a second level overlaying said first level, said second level comprises a plurality of second transistors;

a third level overlaying said second level, said third level comprises a plurality of third transistors;

a first metal layer interconnecting said plurality of first transistors;

a second metal layer overlaying said third level,

wherein said second level has a first coefficient of thermal expansion; and

a connection path connecting at least one of said second transistors to said first metal layer,

wherein said connection path comprises at least one through-layer via,

wherein said through-layer via comprises a material, said material has a second co-efficient of thermal expansion,

wherein said second co-efficient of thermal expansion is within 50 percent of said first coefficient of thermal expansion,

wherein at least one of said plurality of first transistors, at least one of said plurality of second transistors and at least one of said plurality of third transistors are aligned to each other with less than 100 nm misalignment, and

wherein at least one of said plurality of second transistors is a junction-less transistor.

16. The device according to claim 15, further comprising:

a third memory cell comprising at least one of said plurality of third transistors;

a second memory cell comprising at least one of said plurality of second transistors; and

a memory periphery circuit comprising at least one of said plurality of first transistors,

wherein said memory periphery circuit controls said third memory cell and second memory cell.

17. The device according to claim 15,

wherein at least one of said plurality of second transistors is connected to at least one of said plurality of third transistors with an ohmic connection.

18. The device according to claim 15,

wherein said at least one through-layer via is formed through and in direct contact with a source or drain of at least one of said plurality of second transistors.

19. The device according to claim 15,

wherein said plurality of second transistors comprise a second gate dielectric;

wherein said plurality of third transistors comprise a third gate dielectric, and

wherein said second gate dielectric and said third gate dielectric are part of the same layer.

20. The device according to claim 15,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors.