MRAM device and method for fabricating the same

• US 10,038,137 B2
• Filed: 09/30/2016
• Issued: 07/31/2018
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Huang, Sheng-Haung, Wang, Hung-Cho, Shen, Kuei-Hung, Lin, Shy-Jay
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US15/281,428
• Publication Number:
  US 20180097175A1
• Time in Patent Office: 669 Days
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a magnetoresistive random access memory (MRAM) device in an insulating layer. The MRAM device includes a first electrode, a magnetic tunnel junction (MTJ) over the first electrode, a second electrode over the MTJ, and an insulating spacer surrounding sidewalls of the first electrode, the MTJ, and the second electrode. Top surfaces of the insulating spacer and the second electrode are exposed from the insulating layer. The semiconductor device structure also includes a conductive pad over the insulating layer and electrically connected to the second electrode. The MTJ is entirely covered by the conductive pad.

Claims

1. A semiconductor device structure, comprising:

a magnetoresistive random access memory (MRAM) device in an insulating layer, comprising;

a first electrode;

a magnetic tunnel junction (MTJ) over the first electrode, wherein the MTJ comprises a tunnel barrier layer encapsulating a free layer;

a second electrode over the MTJ; and

an insulating spacer surrounding sidewalls of the MTJ and the second electrode, wherein top surfaces of the insulating spacer and the second electrode are exposed from the insulating layer; and

a conductive pad over the insulating layer and electrically connected to the second electrode, wherein the MTJ is entirely covered by the conductive pad.

2. The semiconductor device structure as claimed in claim 1, wherein the conductive pad has a width greater than a width of the MTJ.

3. The semiconductor device structure as claimed in claim 1, wherein the conductive pad is in direct contact with the second electrode.

4. The semiconductor device structure as claimed in claim 1, wherein the MTJ further comprises:

a pinned layer electrically connected to the first electrode;

the free layer over the pinned layer; and

a conductive cap over the free layer, wherein the conductive cap and the pinned layer are isolated from the free layer by the tunnel barrier layer.

5. The semiconductor device structure as claimed in claim 1, wherein the conductive pad extends onto a top surface of the insulating layer.

6. The semiconductor device structure as claimed in claim 1, wherein the MTJ has a tapered sidewall.

7. The semiconductor device structure as claimed in claim 1, further comprising:

a first conductive feature under and electrically connected to the first electrode of the MRAM device; and

a second conductive feature over and electrically connected to the conductive pad.

8. The semiconductor device structure as claimed in claim 7, wherein the first conductive feature is entirely covered by the conductive pad.

9. The semiconductor device structure as claimed in claim 7, wherein the MTJ, the first conductive feature, and the second conductive feature are vertically aligned with each other.

10. The semiconductor device as claimed in claim 7, wherein the MTJ is laterally spaced apart from the first conductive feature.

11. A semiconductor device structure, comprising:

a first conductive feature;

a magnetoresistive random access memory (MRAM) device in an insulating layer and over the first conductive feature, comprising;

a first electrode electrically connected to the first conductive feature;

a magnetic tunnel junction (MTJ) over the first electrode;

a second electrode over the MTJ, wherein top surfaces of the insulating spacer, the second electrode, and the insulating layer are substantially level with each other; and

an insulating spacer surrounding sidewalls of the MTJ and the second electrode;

a conductive pad over the insulating layer and the MRAM device, and electrically connected to the second electrode, wherein the conductive pad has a width greater than a width of the MTJ, such that the MTJ is entirely covered by the conductive pad; and

a second conductive feature over and electrically connected to the conductive pad.

12. The semiconductor device structure as claimed in claim 11, wherein the MTJ is laterally spaced apart from the first conductive feature.

13. The semiconductor device structure as claimed in claim 11, wherein the MTJ, the first conductive feature, and the second conductive feature are vertically aligned with each other.

14. The semiconductor device structure as claimed in claim 11, wherein the conductive pad is in direct contact with the second electrode.

15. The semiconductor device structure as claimed in claim 11, wherein the conductive pad has a thickness in a range of about 50 nm to 250 nm.

16. A method for forming a semiconductor structure, comprising:

forming a magnetoresistive random access memory (MRAM) device over a first conductive feature, wherein the MRAM device comprises;

a first electrode electrically connected to the first conductive feature;

a magnetic tunnel junction (MTJ) over the first electrode;

a second electrode over the MTJ; and

an insulating spacer surrounding sidewalls of the MTJ and the second electrode, wherein the formation of the MRAM device comprises forming a nitride layer over the second electrode before the insulating spacer is formed;

forming an insulating layer covering the nitride layer and the MRAM device;

polishing the insulating layer and the nitride layer to expose a top surface of the second electrode, thereby forming an oxide layer over the second electrode;

removing the oxide layer; and

forming a conductive pad over the second electrode; and

forming a second conductive feature over and electrically connected to the conductive pad.

17. The method as claimed in claim 16, wherein the conductive pad has a width greater than a width of the MTJ.

18. The method as claimed in claim 16, wherein the top surfaces of the second electrode and the insulating spacer are exposed from and substantially level with a top surface of the insulating layer.

19. The method as claimed in claim 16, wherein the oxide layer is a tantalum oxide layer.

20. The method as claimed in claim 16, further comprising:

forming a tantalum layer over the nitride layer before the insulating spacer is formed and removing the tantalum layer after the insulating spacer is formed, such that the insulating spacer is formed on sidewalls of the nitride layer.