Peaking inductor array for peaking control unit of transceiver

• US 10,038,468 B2
• Filed: 08/08/2017
• Issued: 07/31/2018
• Est. Priority Date: 08/03/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Francese, Pier A., Prasad, Mangal, Tran, Hung H., Yuan, Xiaobin
• Primary Examiner(s): Takaoka, Dean
• Assistant Examiner(s): Wong, Alan
• Application Number:
  US15/671,408
• Publication Number:
  US 20170331510A1
• Time in Patent Office: 357 Days
• Field of Search: 333213-215
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03H 11/48 simulating reactances
• CPC Class Codes: H04B 1/12 Neutralising, balancing, or compensation arrangements
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04L 25/03 Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Abstract

Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.

Claims

1. A peaking control unit of a transceiver, comprising:

a linear equalizer;

a direct current (DC) diode array; and

a peaking inductor array connected in parallel with the DC diode array, the peaking inductor array comprising;

a plurality of cells connected in parallel, wherein each cell comprises a respective active inductor, a respective decoupling capacitor, and a respective selectable resistor,

wherein each respective active inductor comprises a respective first field effect transistor (FET) in series with a respective second FET, wherein the respective decoupling capacitor and the respective selectable resistor in each cell are connected in series and are each connected in parallel with the respective first FET, and wherein a capacitance of the respective decoupling capacitor in each cell is larger than intrinsic and extrinsic capacitances of the respective active inductor, and

wherein each respective selectable resistor comprises a respective switch in series with a respective resistor, wherein each respective switch is opened or closed to control peaking of the peaking inductor array in two dimensions.