Circuit for and method of routing data between die of an integrated circuit

• US 10,038,647 B1
• Filed: 05/13/2016
• Issued: 07/31/2018
• Est. Priority Date: 05/13/2016
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lesea, Austin H.
• Primary Examiner(s): Clawson, Stephen J
• Application Number:
  US15/154,892
• Time in Patent Office: 809 Days
• Field of Search: 370359
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules

Abstract

A circuit for routing data between die of an integrated circuit is described. The circuit comprises differential transmitter and receiver pairs of different integrated circuit die that are coupled together by differential transmission lines. A separate differential transmitter associated with the first die of the integrated circuit and a separate differential receiver associated with the second die of the integrated circuit are configured to transmit data day way of the differential transmission lines associated with the differential transmitter and receiver pairs.

Claims

1. A circuit for routing data between die of an integrated circuit, the circuit comprising:

a first differential transmitter and receiver pair having a first differential transmitter associated with a first die of the integrated circuit and a first differential receiver associated with a second die of the integrated circuit, wherein the first differential transmitter has a first output resistor divider coupled between a first output and a second output and the first differential receiver has a first input resistor divider coupled between a first input and a second input;

a first differential transmission line coupled between the first differential transmitter and the first differential receiver;

a second differential transmitter and receiver pair having a second differential transmitter associated with the first die of the integrated circuit and a second differential receiver associated with the second die of the integrated circuit, wherein the second differential transmitter has a second output resistor divider coupled between a third output and a fourth output and the second differential receiver has a second input resistor divider coupled between a third input and a fourth input;

a second differential transmission line coupled between the second differential transmitter and the second differential receiver;

a third differential transmitter associated with the first die of the integrated circuit, the third differential transmitter having a fifth transmitter output coupled to a node of the first output resistor divider and a sixth transmitter output coupled to a node of the second output resistor divider; and

a third differential receiver associated with the second die of the integrated circuit, the third differential receiver having a fifth receiver input coupled to a node of the first input resistor divider and a sixth receiver input coupled to a node of the second input resistor divider.

2. The circuit of claim 1 wherein the third differential transmitter comprises a third output resistor divider, the circuit further comprising a fourth differential transmitter having a first output coupled to a node of the third output resistor divider.

3. The circuit of claim 2 wherein the third differential receiver comprises a third input resistor divider, the circuit further comprising a fourth differential receiver having a first input coupled to a node of the third input resistor divider.

4. The circuit of claim 1 wherein the first, second and third differential transmitters are formed in the first die and the first, second and third differential receivers are formed in the second die.

5. The circuit of claim 1 further comprising a plurality of substrate interconnect elements formed in the substrate, wherein the first, second and third differential transmitters are connected to the first, second and third differential receivers by way of the substrate interconnect elements.

6. The circuit of claim 5 wherein the first, second and third differential transmitters and the first, second and third differential receivers are formed in the substrate.

7. The circuit of claim 1 further comprising an interposer formed on a substrate, wherein the first, second and third differential transmitters and the first, second and third differential receivers are formed in the interposer.

8. The circuit of claim 7 further comprising interposer interconnect elements, wherein the first, second and third differential transmitters are connected to the first, second and third differential receivers by way of the interposer interconnect elements.

9. The circuit of claim 1 further comprising programmable interconnect elements, wherein the programmable interconnect elements enable selectively connecting to outputs of the first, second and third differential transmitters and to inputs of the first, second and third differential receivers.

10. The circuit of claim 1 wherein the first die comprises a memory and the second die comprises a programmable logic device.

11. A method of routing data between die of an integrated circuit, the method comprising:

coupling a first output resistor divider between a first output and a second output of a first differential transmitter associated with a first die;

coupling a first input resistor divider between a first input and a second input of a first differential receiver associated with a second die;

configuring a first differential transmission line between the first differential transmitter and the first differential receiver;

coupling a second output resistor divider between a third output and a fourth output of a second differential transmitter associated with the first die;

coupling a second input resistor divider between a third input and a fourth input of a second differential receiver associated with the second die;

configuring a second differential transmission line between the second differential transmitter and the second differential receiver;

implementing a third differential transmitter associated with the first die of the integrated circuit, the third differential transmitter having a fifth transmitter output coupled to a node of the first output resistor divider and a sixth transmitter output coupled to a node of the second output resistor divider; and

implementing a third differential receiver associated with the second die of the integrated circuit, the third differential receiver having a fifth receiver input coupled to a node of the first input resistor divider and a sixth receiver input coupled to a node of the second input resistor divider.

12. The method of claim 11 wherein implementing the third differential transmitter comprises configuring a third output resistor divider between the fifth output and the sixth output, the method further comprising implementing a fourth differential transmitter having a first output coupled to a node of the third output resistor divider.

13. The method of claim 11 wherein implementing the third differential receiver further comprises configuring a third input resistor divider, the method further comprising configuring a fourth differential receiver having a first input coupled to a node of the third input resistor divider.

14. The method of claim 11 further comprising forming the first, second and third differential transmitters in the first die and forming the first, second and third differential receivers in the second die.

15. The method of claim 11 further comprising configuring a plurality of substrate interconnect elements formed in the substrate, wherein the first, second and third differential transmitters are connected to the first, second and third differential receivers by way of the substrate interconnect elements.

16. The method of claim 15 further comprising implementing the first, second and third differential transmitters and the first, second and third differential receivers in the substrate.

17. The method of claim 11 further comprising implementing an interposer on a substrate, wherein the first, second and third differential transmitters and the first, second and third differential receivers are formed in the interposer.

18. The method of claim 11 further comprising configuring interposer interconnect elements, wherein the first, second and third differential transmitters are connected to the first, second and third differential receivers by way of the interposer interconnect elements.

19. The method of claim 11 further comprising implementing programmable interconnect elements, wherein the programmable interconnect elements enable selectively connecting outputs of the first, second and third differential transmitters to inputs of the first, second and third differential receivers.

20. The method of claim 11 wherein the first die comprises a memory and the second die comprises a programmable logic device.