Array substrate, manufacturing and driving methods thereof, and display device

• US 10,042,461 B2
• Filed: 09/18/2015
• Issued: 08/07/2018
• Est. Priority Date: 02/02/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Liu, Yingming, Dong, Xue, Wang, Haisheng, Chen, Xiaochuan, Ding, Xiaoliang, Yang, Shengji, Zhao, Weijie, Liu, Hongjuan, Li, Changfeng, Liu, Wei
• Primary Examiner(s): Reed, Stephen T
• Application Number:
  US14/913,790
• Publication Number:
  US 20160357314A1
• Time in Patent Office: 1,054 Days
• Field of Search: None
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G06F 2203/04103 Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
• CPC Class Codes: G06F 2203/04111 Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G06F 3/045 using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

An array substrate, manufacturing and driving methods thereof, and a display device are provided. The array substrate includes a base substrate and a plurality of gate lines and a plurality of data lines disposed on the base substrate. A plurality of pixel units distributed in an array are defined by the gate lines and the data lines; each pixel unit includes a common electrode, a pixel electrode and a thin-film transistor (TFT); a first insulating layer is disposed on one side of a layer provided with the common electrodes away from the base substrate; and a plurality of self-capacitance electrodes are disposed on one side of the first insulating layer away from the base substrate.

Claims

1. An array substrate, comprising a base substrate and a plurality of gate lines and a plurality of data lines disposed on the base substrate, wherein

a plurality of pixel units distributed in an array is defined by the gate lines and the data lines;

each pixel unit includes a common electrode, a pixel electrode and a thin-film transistor (TFT);

a first insulating layer is disposed on one side, away from the base substrate, of a layer provided with the common electrodes; and

a plurality of self-capacitance electrodes is disposed on one side, away from the base substrate, of the first insulating layer,

wherein each self-capacitance electrode includes at least one first extension extending along a first direction and at least one second extension extending along a second direction, and the first direction is intercrossed with the second direction;

wherein each first extension is overlapped with and lies within one gate line in a direction perpendicular to the base substrate;

wherein the array substrate further comprises a protection layer disposed on the self-capacitance electrodes, and the protection layer and the pixel electrode are arranged in a same layer and formed with a same material;

wherein each self-capacitance electrode is electrically connected with a lead which is configured to lead out a signal of the self-capacitance electrode, the self-capacitance electrode and the lead are arranged in different layers, a second insulating layer is disposed between a layer provided with the self-capacitance electrode and the lead, and the self-capacitance electrode is electrically connected with the lead via a through hole; and

wherein the array substrate further comprises a conducting block that is disposed on the lead and electrically connected to the lead, the self-capacitance electrode and the lead are electrically connected with each other through the through hole and the conducting block, the TFT includes a first electrode and a second electrode, and the lead and the first electrode are arranged in a same first layer while the conducting block and the second electrode are arranged in a same second layer.

2. The array substrate according to claim 1, wherein the self-capacitance electrodes are disposed between a layer provided with common electrodes and a layer provided with pixel electrodes;

or the self-capacitance electrodes are disposed on one side, away from the base substrate, of the layer provided with the pixel electrodes.

3. The array substrate according to claim 2, wherein the protection layer is disposed on the self-capacitance electrodes in a case where the self-capacitance electrodes are disposed on one side, away from the base substrate, of the layer provided with the pixel electrodes or where the self-capacitance electrodes and the pixel electrodes are arranged side by side on the same layer.

4. The array substrate according to claim 1, wherein each second extension is overlapped with and lies within one data line in the direction perpendicular to the base substrate.

5. The array substrate according to claim 1, wherein the common electrode is provided with a hollowed-out area at a position corresponding to one part of or all the first extension and the second extension of each self-capacitance electrode.

6. The array substrate according to claim 1, wherein the self-capacitance electrode is overlapped with at least one lead electrically connected with other self-capacitance electrode;

a recess is formed in the second insulating layer between the self-capacitance electrode and the lead; and

the depth of the recess is less than the thickness of the second insulating layer.

7. The array substrate according to claim 1, wherein the common electrode is provided with an opening at a position corresponding to the through hole;

and the through hole runs through the opening.

8. The array substrate according to claim 7, wherein a third insulating layer is disposed between the layer provided with the common electrode and the TFT, the TFT includes a gate insulating layer, and the second insulating layer further includes the third insulating layer and the gate insulating layer.

9. The array substrate according to claim 7, wherein a pixel unit group is defined by every two adjacent rows of pixel units;

two gate lines are disposed between the two adjacent rows of pixel units; and

the leads are disposed at gaps between adjacent pixel unit groups.

10. The array substrate according to claim 1, wherein a third insulating layer is disposed between the TFT and the layer provided with the common electrode.

11. A display device, comprising the array substrate according to claim 1.

12. The display device according to claim 11, further comprising:

an opposing substrate arranged opposite to the array substrate,

wherein the opposing substrate is provided with black matrixes, and the first extension and the second extension correspond to positions of the black matrixes in a case where each self-capacitance electrode includes at least one first extension extending along a first direction and/or at least one second extension extending along a second direction, and the first direction is intercrossed with the second direction.

13. A method for manufacturing an array substrate, comprising:

forming a plurality of gate lines, a plurality of data lines, thin film transistors (TFTs), common electrodes, and pixel electrodes on a base substrate;

forming a first insulating layer on one side, away from the base substrate, of the common electrode by one patterning process; and

forming a plurality of self-capacitance electrodes on one side, away from the base substrate, of the first insulating layer by one patterning process,

wherein a plurality of pixel units distributed in an array is defined by the gate lines and the data lines and each pixel unit includes a TFT, a common electrode and a pixel electrode,

wherein each self-capacitance electrode includes at least one first extension extending along a first direction and at least one second extension extending along a second direction, and the first direction is intercrossed with the second direction;

wherein each first extension is overlapped with and lies within one gate line in a direction perpendicular to the base substrate; and

wherein a protection layer is disposed on the self-capacitance electrodes, and the protection layer and the pixel electrode are arranged in a same layer and formed with a same material;

wherein each self-capacitance electrode is electrically connected with a lead which is configured to lead out a signal of the self-capacitance electrode, the self-capacitance electrode and the lead are arranged in different layers, a second insulating layer is disposed between a layer provided with the self-capacitance electrode and the lead, and the self-capacitance electrode is electrically connected with the lead via a through hole; and

wherein the array substrate further comprises a conducting block that is disposed on the lead and electrically connected to the lead, the self-capacitance electrode and the lead are electrically connected with each other through the through hole and the conducting block, the TFT includes a first electrode and a second electrode, and the lead and the first electrode are arranged in a same first layer while the conducting block and the second electrode are arranged in a same second layer.

14. A method for driving an array substrate, comprising:

applying common electrode signals to common electrodes, and applying driving signals to self-capacitance electrodes, receiving feedback signals of the self-capacitance electrodes, and determining a touch position according to the feedback signals;

or

dividing time for displaying one frame into a display period and a touch period, applying common electrode signals to the common electrodes in the display period and the touch period, and in the touch period, applying driving signals to the self-capacitance electrodes, receiving feedback signals of the self-capacitance electrodes, and determining the touch position according to the feedback signals;

wherein both the common electrodes and the self-capacitance electrodes are disposed on the base substrate of the array substrate, a first insulating layer is disposed on one side, away from the base substrate, of the layer provided with the common electrodes, and the self-capacitance electrodes are disposed on one side, away from the base substrate, of the first insulating layer;

wherein each self-capacitance electrode includes at least one first extension extending along a first direction and at least one second extension extending along a second direction, and the first direction is intercrossed with the second direction;

wherein each first extension is overlapped with and lies within one gate line in a direction perpendicular to the base substrate;

wherein the array substrate further comprises a protection layer disposed on the self-capacitance electrodes, and the protection layer and the pixel electrode are arranged in a same layer and formed with a same material;

wherein each self-capacitance electrode is electrically connected with a lead which is configured to lead out a signal of the self-capacitance electrode, the self-capacitance electrode and the lead are arranged in different layers, a second insulating layer is disposed between a layer provided with the self-capacitance electrode and the lead, and the self-capacitance electrode is electrically connected with the lead via a through hole; and

wherein the array substrate further comprises a conducting block that is disposed on the lead and electrically connected to the lead, the self-capacitance electrode and the lead are electrically connected with each other through the through hole and the conducting block, the TFT includes a first electrode and a second electrode, and the lead and the first electrode are arranged in a same first layer while the conducting block and the second electrode are arranged in a same second layer.