Electronic device and operating method thereof

• US 10,042,588 B2
• Filed: 03/23/2017
• Issued: 08/07/2018
• Est. Priority Date: 07/12/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Kang, Jae-Yong
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Chen, Xiaochun L
• Application Number:
  US15/467,374
• Publication Number:
  US 20180018134A1
• Time in Patent Office: 502 Days
• Field of Search: 365158
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Abstract

Disclosed is an operating method of an electronic device which includes a semiconductor memory having a plurality of resistive storage cells. The operating method may include: writing data to the resistive storage cells using a write current of a set condition; determining whether the writing of data to the resistive storage cells is successful, wherein the writing of data is determined to be failed when the number of resistive storage cells with failed writing of data exceeds a reference value, and successful when the number of resistive storage cells with failed writing of data is equal to or less than the reference value; strengthening the set condition when the writing of data is determined to be failed; and easing the set condition when the writing of data is determined to be successful.

Claims

1. An electronic device comprising a semiconductor memory,

wherein the semiconductor memory comprises:

a plurality of resistive storage cells, each operable to store data and to receive a writing current to write data;

a fail bit counter configured to count the number of resistive storage cells in which data are not normally written, among the plurality of resistive storage cells, and determine a write operation as a fail when the count value exceeds a reference value or determine the write operation as a pass when the count value is equal to or less than the reference value;

a set information generation unit configured to generate set information corresponding to a set condition, and update the set information to strengthen the set condition when the determination result is the fail or update the set information to ease the set condition when the determination result is the pass; and

a write current generation unit configured to control a pulse width or an amount of a write current flowing through a resistive storage cell among the plurality of resistive storage cells, according to the set condition,

wherein the electronic device further comprises an optimum condition storage unit configured to store the set information corresponding to the set condition of a current write operation as optimum condition information, when the previous write operation is determined as the fail and the current write operation is determined as the pass, and store the set information corresponding to the set condition of the previous write operation as the optimum condition information, when the previous write operation is determined as the pass and the current write operation is determined as the fail.

2. The electronic device of claim 1, wherein the set information generation unit stores the set information corresponding to the set condition of the previous write operation, until the current write operation is completed.

3. The electronic device of claim 1, wherein the write current generation unit generates a write current using the optimum condition information stored in the optimum condition storage unit, in order to perform a write operation.

4. The electronic device of claim 1, wherein as the set condition is strengthened, the write current generation unit increases the pulse width of the write current, increases the amount of the write current, or increases the pulse width and amount of the write current.

5. The electronic device of claim 1, wherein as the set condition is strengthened, the write current generation unit increases a value corresponding to the product of the pulse width and the current amount.

6. The electronic device of claim 1, wherein as the set condition is eased, the write current generation unit decreases the pulse width of the write current, decreases the amount of the write current, or decreases the pulse width and amount of the write current.

7. The electronic device of claim 1, wherein as the set condition is eased, the write current generation unit decreases a value corresponding to the product of the pulse width and the current amount.

8. The electronic device of claim 1, wherein the semiconductor memory further comprises:

one or more bit lines each coupled to one end of a corresponding resistive storage cell among the plurality of resistive storage cells;

one or more source lines each coupled to the other end of a corresponding resistive storage cell among the plurality of resistive storage cells; and

one or more word lines each coupled to a corresponding resistive storage cell among the plurality of resistive storage cells.

9. The electronic device of claim 8, wherein the write current generation unit increases the period in which a write voltage is applied between the one or more bit lines and source lines when the pulse width of the write current is increased, and decreases the period in which the write voltage is applied between the one or more bit lines and source lines when the pulse width of the write current is decreased.

10. The electronic device of claim 8, wherein when the amount of the write current is increased, the write current generation unit raises the level of a write voltage applied between the one or more bit lines and source lines, raises the level of an active voltage applied to the word line, or raises the level of the write voltage and the level of the active voltage.

11. The electronic device of claim 8, wherein when the amount of the write current is decreased, the write current generation unit lowers the level of a write voltage applied between the one or more bit lines and source lines, lowers the level of an active voltage applied to the word line, or lowers the level of the write voltage and the level of the active voltage.

12. The electronic device of claim 1, wherein the variable resistance element comprises one or more of structures each having a tunnel barrier layer interposed between two magnetic layers.

13. The electronic device of claim 1, further comprising a microprocessor,

wherein the microprocessor comprising:

an access control unit suitable for receiving a signal having a command from an outside of the microprocessor, extracting or decoding the command, or performing input/output control of the signal of the microprocessor;

an operation unit suitable for performing an operation according to a decoding result of the command in the access control unit; and

a storage unit suitable for storing data to be operated, data corresponding to an operation result, or an address of the data to be operated, and

wherein the semiconductor memory is a part of the storage unit within the microprocessor.

14. The electronic device of claim 1, further comprising a processor,

wherein the processor comprising:

a core unit suitable for performing an operation corresponding to a command using data according to the command input from an outside of the processor;

a cache memory unit suitable for storing data to be operated, data corresponding to an operation result, or an address of the data to be operated; and

a bus interface which is coupled between the core unit and the cache memory unit, and transfers data between the core unit and the cache memory unit, and

wherein the semiconductor memory is a part of the cache memory unit within the processor.

15. The electronic device of claim 1, further comprising a processing system, and

wherein the processing system comprising:

a processor suitable for interpreting a received command, and controlling an operation of information according to an interpreting result of the command;

an auxiliary memory device suitable for storing a program for interpreting the command and the information;

a main memory device suitable for importing and storing the program and the information from the auxiliary memory device such that the processor performs the operation using the program and the information when the program is executed; and

an interface device suitable for performing communication between one or more of the processor, the auxiliary memory device and the main memory device and an outside, and

wherein the semiconductor memory is a part of the auxiliary memory device or the main memory device within the processing system.

16. The electronic device of claim 1, further comprising a data storage system,

wherein the data storage system comprising:

a storage device suitable for storing data and retaining the stored data regardless of a power supply;

a controller suitable for controlling data input/output of the storage device according to a command input from an outside;

a temporary storage device suitable for temporarily storing the data which is exchanged between the storage device and the outside; and

an interface suitable for performing communication between one or more of the storage device, the controller and the temporary storage device and the outside, and

wherein the semiconductor memory is a part of the storage device or the temporary storage device within the data storage system.

17. The electronic device of claim 1, further comprising a memory system,

wherein the memory system comprising:

a memory suitable for storing data and retaining the stored data regardless of a power supply;

a memory controller suitable for controlling data input/output of the memory according to a command input from an outside;

a buffer memory suitable for buffering the data which is exchanged between the memory and the outside; and

an interface suitable for performing communication between one or more of the memory, the memory controller and the buffer memory and the outside, and

wherein, the semiconductor memory is a part of the memory or the buffer memory within the memory system.