Method and apparatus for asynchronous processor with auxiliary asynchronous vector processor

• US 10,042,641 B2
• Filed: 09/08/2014
• Issued: 08/07/2018
• Est. Priority Date: 09/06/2013
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Zhang, Qifan, Shi, Wuxian, Ge, Yiqun, Huang, Tao, Tong, Wen
• Primary Examiner(s): Xiao, Yuqing
• Application Number:
  US14/480,573
• Publication Number:
  US 20150074374A1
• Time in Patent Office: 1,429 Days
• Field of Search: 712 7, 712 24, 712 10, 712 21, 712 22, 712 31, 712 34
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 2009/3883 Two-engine architectures, i.e. stand-alone processor acting as a slave processor
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3871 Asynchronous instruction pipeline, e.g. using handshake signals between stages
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

An asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the scalar processor. The asynchronous scalar processor is configured to perform processing functions on input data and to output instructions. The asynchronous vector processor is configured to perform processing functions in response to a very long instruction word (VLIW) received from the scalar processor. The VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.

Claims

1. A method of operating an asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the asynchronous scalar processor, the asynchronous vector processor comprising a plurality of parallel asynchronous vector execution units (VXU), the method comprising:

performing processing functions on input data at the asynchronous scalar processor and sending a very long instruction word (VLIW) to the asynchronous vector processor;

generating, by the parallel asynchronous VXU, an instruction execution result corresponding to the VLIW;

storing, in a register file, the instruction execution result generated by the parallel asynchronous VXU;

storing, in a history table, a time at which a register within the register file was last modified; and

detecting a data dependency via the history table based on the time at which the register within the register file was last modified.

2. The method in accordance with claim 1, further comprising:

storing the instruction execution result in a crossbar coupled to each parallel asynchronous VXU.

3. The method in accordance with claim 2, further comprising:

in response to a first vector execution result being currently stored in the crossbar, obtaining by a given parallel asynchronous VXU the first vector execution result from the crossbar and bypassing a fetch operation for the first vector execution result in the register file; and

in response to the first vector execution result being not currently stored in the crossbar, obtaining by the given parallel asynchronous VXU the first vector execution result from the register file.

4. The method in accordance with claim 1, wherein:

each parallel asynchronous VXU comprises token processing logic configured to receive, hold and pass a token from one parallel asynchronous VXU to another parallel asynchronous VXU; and

the token processing logic comprises a token signal path in the plurality of parallel asynchronous VXUs to enable propagation of the token through the plurality of parallel asynchronous VXUs, wherein possession of the token by one of the parallel asynchronous VXUs enables that parallel asynchronous VXU to conduct a transaction with a resource component that is shared among the plurality of parallel asynchronous VXUs.

5. The method in accordance with claim 1, further comprising:

decoding, by each of a plurality of decoders in each of the parallel asynchronous VXUs, a respective portion of the VLIW.

6. The method in accordance with claim 1, further comprising:

returning the instruction execution result from the asynchronous vector processor to the asynchronous scalar processor.

7. The method in accordance with claim 1, wherein the VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.

8. The method in accordance with claim 1, further comprising executing, by the parallel asynchronous VXU, three sub-instructions within the VLIW.

9. An asynchronous processing system comprising:

an asynchronous scalar processor configured to perform processing functions on input data and to output instructions;

an asynchronous vector processor coupled to the asynchronous scalar processor and configured to perform processing functions on a very long instruction word (VLIW) received from the asynchronous scalar processor;

the asynchronous vector processor comprising;

a plurality of parallel asynchronous vector execution units (VXU), each parallel asynchronous VXU configured to generate an instruction execution result;

a register file configured to store the instruction execution result generated from each parallel asynchronous VXU; and

a vector instruction fetch (VIF) block comprising an instruction dispatcher having a history table, the VIF block configured to receive the VLIW from the asynchronous scalar processor, the history table configured to store a time at which a register within the register file was last modified, and the instruction dispatcher configured to detect a data dependency via the history table based on the time at which the register within the register file was last modified.

10. The asynchronous processing system in accordance with claim 9, wherein the asynchronous vector processor further comprises:

a crossbar coupled to each parallel asynchronous VXU and to the VIF block, the crossbar configured to store the instruction execution result generated by each parallel asynchronous VXU.

11. The asynchronous processing system in accordance with claim 10, wherein:

in response to a first vector execution result being currently stored in the crossbar, a given asynchronous parallel VXU is configured to obtain the first vector execution result from the crossbar and bypass a fetch operation for the first vector execution result in the register file; and

in response to the first vector execution result being not currently stored in the crossbar, the given asynchronous parallel VXU is configured to obtain the first vector execution result from the register file.

12. The asynchronous processing system in accordance with claim 9, wherein each parallel asynchronous VXU comprises token processing logic configured to receive, hold and pass a token from one parallel asynchronous VXU to another parallel asynchronous VXU;

and

wherein the token processing logic comprises a token signal path in the plurality of parallel asynchronous VXUs to enable propagation of the token through the plurality of parallel asynchronous VXUs, wherein possession of the token by one of the parallel asynchronous VXUs enables that parallel asynchronous VXU to conduct a transaction with a resource component that is shared among the plurality of parallel asynchronous VXUs.

13. The asynchronous processing system in accordance with claim 12, wherein the token processing logic is configured to propagate the token at a propagation rate that is related to a latency associated with the parallel asynchronous VXU.

14. The asynchronous processing system in accordance with claim 13, wherein the latency is variable and is based on an operation to be conducted by the parallel asynchronous VXU.

15. The asynchronous processing system in accordance with claim 9, wherein each parallel asynchronous VXU comprising a plurality of decoders, each decoder corresponding to a respective portion of the VLIW.

16. The asynchronous processing system in accordance with claim 9, wherein the asynchronous processing system further comprises:

a register return port coupled to the asynchronous scalar processor and the asynchronous vector processor, the register return port configured to return the instruction execution result from the asynchronous vector processor to the asynchronous scalar processor.

17. The asynchronous processing system in accordance with claim 9, wherein the VIF block further comprises:

an instruction first in first out (FIFO) memory configured to receive and store the VLIW from the asynchronous scalar processor; and

an instruction pre-decoder processor configured to pre-process the VLIW.

18. The asynchronous processing system in accordance with claim 9, wherein the register file is coupled to each parallel asynchronous VXU and to the VIF block.

19. The asynchronous processing system in accordance with claim 9, wherein the VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.

20. The asynchronous processing system in accordance with claim 9, wherein each parallel asynchronous VXU is further configured to execute three sub-instructions within the VLIW.