Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor
First Claim
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1. An apparatus, comprising:
- a processing unit configured to run an operating system, wherein the operating system is a memory management hypervisor (MATH) operating system, wherein the MMH operating system provides memory management threads (MMT) configured to manage the memory, wherein the MMH operating system is configured to support a guest operating system run on the processing unit;
a memory coupled to the processing unit, the memory configured to communicate with the processing unit via a memory bus, wherein the memory includes a first memory controller configured to access at least one of a volatile memory or a non-volatile memory; and
an adaptive memory controller configured to receive monitored statistical data from the first memory controller and from the processing unit, wherein the adaptive memory controller is configured to manage the memory based on the monitored statistical data, wherein the adaptive memory controller comprises a memory management processor (MMP) configured to run the MMT, wherein the MMP running the MMT is configured to manage the memory based on the monitored statistical data, wherein the MMP is configured to at least one of;
change a frequency of a portion of the at least one of the non-volatile memory or the volatile memory;
change a refresh period of a portion of the volatile memory;
perform a memory scrub of a portion of the at least one of the non-volatile memory or the volatile memory;
orchange a multi-level cell mode of a portion of the at least one of the non-volatile memory or the volatile memory.
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Abstract
Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.
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Citations
27 Claims
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1. An apparatus, comprising:
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a processing unit configured to run an operating system, wherein the operating system is a memory management hypervisor (MATH) operating system, wherein the MMH operating system provides memory management threads (MMT) configured to manage the memory, wherein the MMH operating system is configured to support a guest operating system run on the processing unit; a memory coupled to the processing unit, the memory configured to communicate with the processing unit via a memory bus, wherein the memory includes a first memory controller configured to access at least one of a volatile memory or a non-volatile memory; and an adaptive memory controller configured to receive monitored statistical data from the first memory controller and from the processing unit, wherein the adaptive memory controller is configured to manage the memory based on the monitored statistical data, wherein the adaptive memory controller comprises a memory management processor (MMP) configured to run the MMT, wherein the MMP running the MMT is configured to manage the memory based on the monitored statistical data, wherein the MMP is configured to at least one of; change a frequency of a portion of the at least one of the non-volatile memory or the volatile memory; change a refresh period of a portion of the volatile memory; perform a memory scrub of a portion of the at least one of the non-volatile memory or the volatile memory;
orchange a multi-level cell mode of a portion of the at least one of the non-volatile memory or the volatile memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method, comprising:
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retrieving, using a memory controller of a memory, information in at one of a non-volatile or volatile memory of the memory responsive to memory access requests received at the memory controller from a processing unit running a memory management hypervisor (MMH) operating system; and managing a configuration of the memory at a memory management processor (MMP) running memory management threads (MMT) of the MMH operating system based on monitored statistical data, including; changing a multi-level cell mode of a portion of memory; managing mingration of information in the memory including managing metadata of page tables and translation lookaside buffers; and responsive to receiving a memory access request for information stored in a portion of the memory undergoing a migration; generating a page fault in the MMH operating system while the requested information is unavailable; and providing the information when the portion of the memory become available. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method comprising:
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retrieving, using a memory controller of a memory, information in at one of a non-volatile or volatile memory of the memory responsive to memory access requests received at the memory controller from a processing unit running a memory management hypervisor (MMH) operating system; and managing a configuration of the memory at a memory management processor (MMP) running memory management threats (MMT) of the MMH operating system based on monitored statistical data, wherein managing migration of information in the memory further comprises; changing a multi-level cell mode of a portion of memory; managing mingration of information in the memory including managing metadata of page tables and translation lookaside buffers; and responsive to receiving a memory access request for information stored in a portion of the memory undergoing a migration; stalling a thread making the request in the MMH operating system while the requested information is unavailable; and providing a translation of a logical address of the memory access request associated with a new address of the memory where the information is stored responsive to completion of movement of the information.
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Specification