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Host controller of high-speed data interface with clock-domain crossing

  • US 10,042,810 B2
  • Filed: 06/02/2016
  • Issued: 08/07/2018
  • Est. Priority Date: 12/07/2015
  • Status: Active Grant
First Claim
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1. A host controller of high-speed data interface, comprising:

  • a logical physical layer and a plurality of electrical physical layers, wherein the logical physical layer provides a plurality of groups of low-speed data, each of the electrical physical layers converts one group of the low-speed data to high-speed data and transmit the high-speed data to one of a plurality of external devices, and each of the electrical physical layers operates according to one of a plurality of clock signals;

    a multiplexer, receiving the plurality of clock signals corresponding to the plurality of electrical physical layers to output a common clock signal for the logical physical layer to provide the plurality of groups of low-speed data based on the common clock signal; and

    a clock-domain-crossing transmitter, coupled between the logical physical layer and the plurality of electrical physical layers, and using the common clock signal to retrieve the plurality of groups of low-speed data provided from the logical physical layer,wherein, with respect to each of the external devices, the clock-domain-crossing transmitter uses the one of the plurality of clock signals corresponding to the electrical physical layer connected to the external device to output the corresponding group of low-speed data to the electrical physical layer connected to the external device.

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