Semiconductor package structure and manufacturing method thereof

• US 10,043,728 B2
• Filed: 02/22/2017
• Issued: 08/07/2018
• Est. Priority Date: 03/04/2016
• Status: Active Grant

• Current Assignee: Niko Semiconductor Co., Ltd
• Original Assignee: Niko Semiconductor Co., Ltd
• Inventors: Hsieh, Chih-Cheng
• Primary Examiner(s): Sullivan, Caleen
• Application Number:
  US15/439,464
• Publication Number:
  US 20170256473A1
• Time in Patent Office: 531 Days
• Field of Search: 257690
• CPC Class Codes: H01L 21/52 Mounting semiconductor bodies in containers
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/8314 Guiding structures outside the body
• CPC Class Codes: H01L 2224/92242 the first connecting process involving a layer connector
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/92 Specific sequence of method steps
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H02P 27/06 using dc to ac converters or inverters H02P27/05 takes precedence

Abstract

A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a second printed circuit board are provided. The first surface mounting unit includes a first chip and a first conductive frame, and the first conductive frame has a first carrier board and a first metal member connected to the first carrier board. A first side of the first chip is electrically connected to the first carrier board of the first conductive frame. A second side of the first chip and the first metal member are connected to the first circuit board by a first pad and a second pad respectively. The second circuit board is connected to the first carrier board and hence, the first surface mounting unit is located between the first circuit board and the second circuit board.

Claims

1. A semiconductor package structure comprising:

a first surface mounting element comprising;

a first conductive frame comprising a first carrier board and a first metal member, the first carrier board and the first metal member connect with each other and form a first receiving area; and

a first chip disposed in the first receiving area, a first side of the first chip is electrically connected to the first carrier board;

a first circuit board engaged with the first surface mounting element, a second side of the first chip and the first metal member are connected to the first circuit board through a first pad and a second pad respectively;

a second circuit board connected to the first carrier board, the first surface mounting element is located between the first circuit board and the second circuit board; and

a closed-loop metal ring disposed between the first circuit board and the second circuit board, the closed-loop metal ring surrounding the first surface mounting element.

2. The semiconductor package structure according to claim 1, wherein the first pad and the second pad are connected to a same surface of the first circuit board.

3. The semiconductor package structure according to claim 1, wherein the first surface mounting element further comprises a first enhancing chip connected to the second side of the first chip through a metal layer on the first circuit board.

4. The semiconductor package structure according to claim 1, wherein the first chip is an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET), and the enhancing chip is a power diode.

5. The semiconductor package structure of claim 1, further comprising:

a second surface mounting element comprising;

a second conductive frame comprising a second carrier board and a second metal member, the second carrier board and the second metal member connect with each other and form a second receiving area; and

a second chip disposed in the second receiving area, a second side of the second chip is electrically connected to the second carrier board;

wherein the second side of the second chip and the second metal member are connected to the first circuit board through a third pad and a fourth pad respectively.

6. The semiconductor package structure according to claim 1, further comprising a first heat dissipation plate and a second heat dissipation plate, the first dissipation plate is connected to the first circuit board, and the second heat dissipation plate is connected to the second circuit board.

7. A semiconductor package structure comprising:

a first surface mounting element comprising;

a first conductive frame comprising a first carrier board and a first metal member, the first carrier board and the first metal member connect with each other and form a first receiving area; and

a first chip disposed in the first receiving area, a first side of the first chip is electrically connected to the first carrier board;

a first circuit board engaged with the first surface mounting element, a second side of the first chip and the first metal member are connected to the first circuit board through a first pad and a second pad respectively;

a second circuit board connected to the first carrier board, the first surface mounting element is located between the first circuit board and the second circuit board; and

a second surface mounting element comprising;

a second conductive frame comprising a second carrier board and a second metal member, the second carrier board and the second metal member connect with each other and form a second receiving area; and

a second chip disposed in the second receiving area, a second side of the second chip is electrically connected to the second carrier board;

wherein the second side of the second chip and the second metal member are connected to the first circuit board through a third pad and a fourth pad respectively.