Packaged microelectronic device for a package-on-package device

• US 10,043,779 B2
• Filed: 11/16/2016
• Issued: 08/07/2018
• Est. Priority Date: 11/17/2015
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Prabhu, Ashok S., Katkar, Rajesh
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US15/353,577
• Publication Number:
  US 20170141083A1
• Time in Patent Office: 629 Days
• Field of Search: 257777, 257686, 257685, 257723, 257738, 257737, 257734, 257778
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/54 Providing fillings in containers, e.g. gas fillings
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/18 : Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15322 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, interconnect structures are in an outer region of the packaged microelectronic device. A microelectronic device is coupled in an inner region of the packaged microelectronic device inside the outer region. A dielectric layer surrounds at least portions of shafts of the interconnect structures and along sides of the microelectronic device. The interconnect structures have first ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.

Claims

1. A method for forming a packaged microelectronic device, comprising:

forming interconnect structures in and coupled to an outer region of a redistribution layer of the packaged microelectronic device;

providing a microelectronic device in and coupled to an inner region of a redistribution layer of the packaged microelectronic device inside the outer region;

forming a dielectric layer surrounding at least portions of shafts of the interconnect structures and along sides of the microelectronic device; and

the interconnect structures having first ends thereof protruding above an upper surface of the dielectric layer a distance and having second ends thereof coupled to the redistribution layer, the first ends and the second ends corresponding thereto facing away from one another.

2. The method according to claim 1, further comprising:

forming the redistribution layer over the second ends of the interconnect structures and over the microelectronic device, the second ends of the interconnect structures being opposite the first ends of the interconnect structures, the redistribution layer including interconnect pads in both the inner region and the outer region along a surface of the redistribution layer.

3. The method according to claim 1, wherein the interconnect structures include plating-formed posts.

4. The method according to claim 1, wherein the interconnect structures include wire bond wires.

5. The method according to claim 1, further comprising forming interconnect pads located on the first ends of the interconnect structures.

6. The method according to claim 1, wherein the packaged microelectronic device is a first packaged microelectronic device, the method further comprising coupling a second packaged microelectronic device to protrusions associated with the first ends of the interconnect structures with electrically conductive bonding masses to provide a package-on-package device.

7. The method according to claim 1, wherein the first ends of at least some of the interconnect structures protruding above the upper surface of the dielectric layer are laterally displaced with respect to corresponding ones of the second ends of the interconnect structures.

8. A packaged microelectronic device, comprising:

interconnect structures in and coupled to an outer region of a redistribution layer of the packaged microelectronic device;

a microelectronic device provided in and coupled to an inner region of a redistribution layer of the packaged microelectronic device inside the outer region; and

a dielectric layer surrounding at least portions of shafts of the interconnect structures and along sides of the microelectronic device;

the interconnect structures having first ends thereof protruding above an upper surface of the dielectric layer a distance and having second ends thereof coupled to the redistribution layer, the first ends and the second ends corresponding thereto facing away from one another.

9. The packaged microelectronic device according to claim 8, further comprising:

the redistribution layer coupled to the second ends of the interconnect structures and over the microelectronic device; and

the redistribution layer comprising interconnect pads in both the inner region and the outer region along a surface of the redistribution layer.

10. The packaged microelectronic device according to claim 8, wherein the interconnect structures include plating-formed posts.

11. The packaged microelectronic device according to claim 8, wherein the interconnect structures include wire bond wires.

12. The packaged microelectronic device according to claim 8, further comprising interconnect pads located on the first ends of the interconnect structures.

13. The packaged microelectronic device according to claim 8, wherein the packaged microelectronic device is a first packaged microelectronic device, and the first packaged microelectronic device further comprising a second packaged microelectronic device directly coupled to protrusions associated with the first ends of the interconnect structures with electrically conductive bonding masses to provide a package-on-package device.

14. The packaged microelectronic device according to claim 8, wherein the first ends of at least some of the interconnect structures protruding above the upper surface of the dielectric layer are laterally displaced with respect to corresponding ones of the second ends of the interconnect structures.

15. The packaged microelectronic device according to claim 8, further comprising a reinforcing layer with a stiffener material beneath the dielectric layer.

16. The packaged microelectronic device according to claim 8, wherein the first ends protrude at least 100 microns beyond the dielectric layer.

17. The packaged microelectronic device according to claim 13, wherein the first ends protrude to a length sufficient to accommodate warpage of the first packaged microelectronic device or the second packaged microelectronic device.