3D semiconductor device and structure

• US 10,043,781 B2
• Filed: 02/25/2018
• Issued: 08/07/2018
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak, Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US15/904,377
• Publication Number:
  US 20180190619A1
• Time in Patent Office: 163 Days
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.

Claims

1. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;

a plurality of second transistors overlaying said first single crystal layer;

at least one connection from said plurality of first transistors to a plurality of through silicon vias (TSVs);

a plurality of third transistors overlaying said plurality of second transistors,

wherein said plurality of second transistors are self-aligned to said plurality of third transistors having been processed following the same lithography step; and

a first memory array and a second memory array,

wherein said first memory array comprises said plurality of second transistors and said second memory array comprises said plurality of third transistors,

wherein at least one of said plurality of second transistors comprises a polysilicon channel,

wherein at least one of said plurality of second transistors is a junction-less transistor, and

wherein each of said plurality of second transistors comprises a gate.

2. The 3D semiconductor device according to claim 1,

wherein formation of said gate comprises an Atomic Layer Deposition (ALD).

3. The 3D semiconductor device according to claim 1, further comprising:

a NAND type flash memory comprising said first memory array.

4. The 3D semiconductor device according to claim 1, further comprising:

a top metal layer overlaying said plurality of third transistors,

wherein a subset of said plurality of first transistors are part of a peripheral circuit controlling said first memory array.

5. The 3D semiconductor device according to claim 1, wherein said plurality of second transistors comprises a gate dielectric, and wherein said gate dielectric comprises a low temperature microwave plasma oxide.

6. The 3D semiconductor device according to claim 1, further comprising:

a staircase structure.

7. The 3D semiconductor device according to claim 1,

wherein at least one of said plurality of second transistors overlays at least partially one of said TSVs.

8. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;

a plurality of second transistors overlaying said first single crystal layer;

at least one connection from said plurality of first transistors to a plurality of through silicon vias (TSVs);

a plurality of third transistors overlaying said plurality of second transistors,

wherein said plurality of second transistors are self-aligned to said plurality of third transistors having been processed following the same lithography step; and

a first memory array and a second memory array,

wherein said first memory array comprises said plurality of second transistors and said second memory array comprises said plurality of third transistors,

wherein at least one of said plurality of second transistors comprises a polysilicon channel,

wherein at least one of said plurality of second transistors is a junction-less transistor, and

said device further comprising;

a first set of external connections underlying said one metal layer to connect said device to a first external device; and

a second set of external connections overlying said one metal layer to connect said device to a second external device,

wherein said first set of external connections comprises said plurality of through silicon vias (TSVs).

9. The 3D semiconductor device according to claim 8,

wherein at least one of said second transistors is a double gate transistor, and

wherein each gate of said double gate transistor is independently controlled.

10. The 3D semiconductor device according to claim 8,

wherein at least one of said second transistors overlays at least partially one of said TSVs.

11. The 3D semiconductor device according to claim 8, further comprising:

a NAND type flash memory comprising said first memory array.

12. The 3D semiconductor device according to claim 8, further comprising:

a top metal layer overlaying said plurality of third transistors, wherein a subset of said plurality of first transistors are part of a peripheral circuit controlling said first memory array.

13. The 3D semiconductor device according to claim 8, further comprising:

a first set of external connections underlying said one metal layer to connect said device to a first external device; and

a second set of external connections overlying said one metal layer to connect said device to a second external device,

wherein said first set of external connections comprises said plurality of through silicon vias (TSVs).

14. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;

a plurality of second transistors overlaying said first single crystal layer;

at least one connection from said plurality of first transistors to a plurality of through silicon vias (TSVs);

a plurality of third transistors overlaying said plurality of second transistors,

wherein said plurality of second transistors are self-aligned to said plurality of third transistors having been processed following the same lithography step; and

a first memory array and a second memory array,

wherein said first memory array comprises said plurality of second transistors and said second memory array comprises said plurality of third transistors.

15. The 3D semiconductor device according to claim 14,

wherein at least one of said plurality of second transistors comprises a polysilicon channel.

16. The 3D semiconductor device according to claim 14,

wherein at least one of said second transistors is a double gate transistor, and

wherein each gate of said double gate transistor is independently controlled.

17. The 3D semiconductor device according to claim 14,

wherein at least one of said second transistors is of the dopant segregated schottky barrier type.

18. The 3D semiconductor device according to claim 14,

wherein at least one of said plurality of second transistors is a junction-less transistor.

19. The 3D semiconductor device according to claim 14, further comprising:

a NAND type flash memory comprising said plurality of second transistors.

20. The 3D semiconductor device according to claim 14, further comprising:

a top metal layer overlaying said plurality of third transistors; and

a plurality of fourth transistors overlaying said top metal,

wherein a subset of said plurality of first transistors are part of a peripheral circuit controlling said first memory array.