Method to induce strain in finFET channels from an adjacent region

• US 10,043,805 B2
• Filed: 06/29/2016
• Issued: 08/07/2018
• Est. Priority Date: 09/16/2013
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Morin, Pierre, Loubet, Nicolas
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): Khan, Farid
• Application Number:
  US15/197,509
• Publication Number:
  US 20160307899A1
• Time in Patent Office: 769 Days
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Claims

1. A device, comprising:

a substrate;

a transistor on the substrate, the transistor including;

a strain-inducing base structure of a first material on the substrate, the strain-inducing base structure having an outer sidewall;

a fin structure of a second material on the strain-inducing base structure, the first material being different than the second material; and

a constraining material on the substrate and on the outer sidewall of the strain-inducing base structure, a top surface of the constraining material being below a top surface of the fin structure, an outer surface of the constraining material being spaced apart from the outer sidewall of the strain-inducing base structure.

2. The device of claim 1 wherein the substrate includes a pedestal and the strain-inducing base structure is on the pedestal of the substrate.

3. The device of claim 2 wherein the substrate has a first surface and a second surface that is a top of the pedestal, the first surface being below the second surface.

4. The device of claim 3 wherein the constraining material is formed on the first surface of the substrate adjacent to sidewalls of the pedestal.

5. The device of claim 1, further comprising a dielectric layer adjacent to sidewalls of the constraining material.

6. The device of claim 5 wherein the dielectric layer is on a first surface of the substrate.

7. A device, comprising:

a substrate having a plurality of raised portions extending above a top surface of the substrate;

a plurality of base structures of a first material, each base structure of the plurality of base structures being formed on one of the plurality of raised portions of the substrate;

a plurality of fins of a second material, the first material being different than the second material, each fin of the plurality of fins formed on one of the plurality of base structures, each fin of the plurality of fins being separated from the substrate by the one of the plurality of base structures;

a plurality of constraining structures formed adjacent to sidewalls of each base structure of the plurality of base structures; and

a dielectric liner layer adjacent to sidewalls of the plurality of constraining structures and on the top surface of the substrate.

8. The device of claim 7 wherein a top surface of each constraining structure of the plurality of constraining structures is below a top surface of each fin of the plurality of fins.

9. The device of claim 7 wherein a top surface of the dielectric liner layer is below a top surface of each fin of the plurality of fins.

10. The device of claim 7, further comprising an insulating layer formed on the dielectric liner layer.

11. The device of claim 7 wherein a first one of the plurality of base structures includes silicon carbide and a second one of the plurality of base structures includes silicon germanium.

12. The device of claim 11 wherein the first one of the plurality of base structures is in a p-type transistor and the second one of the plurality of base structures is in an n-type transistor.

13. A device, comprising:

a substrate having a first surface and a plurality of pedestals that extend away from the first surface, each pedestal of the plurality of pedestals having a second surface;

a plurality of first structures of a first material, each first structure of the plurality of first structures being formed on the second surface of a respective pedestal of the plurality of pedestals, each first structure of the plurality of first structures having a first surface transverse to the second surface of the respective pedestal;

a plurality of second structures of a second material, the first material being different than the second material, each second structure of the plurality of second structures being formed on one first structure of the plurality of first structures, each second structure of the plurality of second structures having a top surface and including a channel of a transistor; and

a plurality of first sidewalls, each first sidewall of the plurality of first sidewalls being formed adjacent to one first structure of the plurality of first structures, each first sidewall of the plurality of first sidewalls including a top surface that is below a top surface of a respective second structure of the plurality of second structures, each first sidewall of the plurality of first sidewalls having a second surface transverse to the top surface, the second surface of each first sidewall of the plurality of first sidewalls being spaced apart from a respective first surface of a respective first structure.

14. The device of claim 13 wherein each first sidewall of the plurality of sidewalls is formed on the first surface of the substrate.

15. The device of claim 14, further comprising a plurality of second sidewalls, each second sidewall of the plurality of second sidewalls being formed adjacent to one first sidewall of the plurality of first sidewalls.

16. The device of claim 15 wherein each second sidewall of the plurality of second sidewalls includes a top surface that is below the top surface of each second structure of the plurality of second structures.