Methods for forming a semiconductor device with a gate stack having angled sidewalls

• US 10,043,887 B2
• Filed: 12/12/2016
• Issued: 08/07/2018
• Est. Priority Date: 09/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Chen, Yi-Jen, Chen, Chang-Yin, Chang, Yung Jung
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): Boulghassoul, Younes
• Application Number:
  US15/376,610
• Publication Number:
  US 20170092741A1
• Time in Patent Office: 603 Days
• Field of Search: 257407, 257411, 257412, 257346, 257387, 257204, 257E2119, 257E29255, 257E21248, 257E21626, 257E21632, 257E2164, 438591, 438302, 438285, 438287, 438283, 438303, 438301, 438595, 438199, 438230
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Claims

1. A method of forming a semiconductor device, comprising:

forming a silicon dummy layer;

etching the silicon dummy layer to define a first tapered sidewall and a second tapered sidewall, comprising;

performing a first etch using a first etch process to etch through a first portion of the silicon dummy layer;

performing a second etch using a second etch process to etch through a second portion of the silicon dummy layer, the second etch process different than the first etch process; and

performing a third etch using a third etch process to etch through a third portion of the silicon dummy layer, wherein the third etch exposes a top surface of a substrate underlying the silicon dummy layer;

forming a first spacer adjacent the first tapered sidewall of the silicon dummy layer and forming a second spacer adjacent the second tapered sidewall of the silicon dummy layer;

removing the silicon dummy layer to form an opening, wherein the opening is defined by a first tapered sidewall of the first spacer previously in contact with the first tapered sidewall of the silicon dummy layer and a first tapered sidewall of the second spacer previously in contact with the second tapered sidewall of the silicon dummy layer; and

forming a gate electrode in the opening.

2. The method of claim 1, wherein the third etch process comprises a flow rate of CF₄ different than a flow rate of CF₄ during the first etch process and different than a flow rate of CF₄ during the second etch process.

3. The method of claim 1, wherein the first etch process comprises a first flow rate of Cl₂ and the second etch process comprises a second flow rate of Cl₂ different than the first flow rate of Cl₂.

4. The method of claim 1, wherein the first etch process comprises a first flow rate of CF₄ and the second etch process comprising a second flow rate of CF₄ different than the first flow rate of CF₄.

5. The method of claim 1, wherein:

the first etch defines a first non-tapered sidewall and a second non-tapered sidewall, and

the second etch tapers the first non-tapered sidewall to define the first tapered sidewall and tapers the second non-tapered sidewall to define the second tapered sidewall.

6. The method of claim 1, wherein, upon forming the first spacer and the second spacer, the first tapered sidewall of the first spacer is in contact with the first tapered sidewall of the silicon dummy layer and the first tapered sidewall of the second spacer is in contact with the second tapered sidewall of the silicon dummy layer.

7. The method of claim 1, comprising forming an interfacial layer in the opening prior to forming the gate electrode, wherein sidewalls of the interfacial layer conform to the first tapered sidewall of the first spacer and the first tapered sidewall of the second spacer.

8. The method of claim 7, comprising forming a gate dielectric in the opening and over the interfacial layer prior to forming the gate electrode, wherein sidewalls of the gate dielectric conform to the first tapered sidewall of the first spacer and the first tapered sidewall of the second spacer.

9. The method of claim 1, comprising forming a gate dielectric in the opening prior to forming the gate electrode, wherein sidewalls of the gate dielectric conform to the first tapered sidewall of the first spacer and the first tapered sidewall of the second spacer.

10. The method of claim 1, wherein sidewalls of the gate electrode conform to the first tapered sidewall of the first spacer and the first tapered sidewall of the second spacer.

11. A method of forming a semiconductor device, comprising:

forming a silicon dummy layer;

etching the silicon dummy layer such that a width of the silicon dummy layer at a top surface of the silicon dummy layer is greater than a width of the silicon dummy layer at a bottom surface of the silicon dummy layer, wherein the etching comprises;

performing a first etch using a first etch process to etch through a first portion of the silicon dummy layer;

performing a second etch using a second etch process to etch through a second portion of the silicon dummy layer, the second etch process different than the first etch process; and

performing a third etch using a third etch process to etch through a third portion of the silicon dummy layer, wherein the third etch exposes a top surface of a substrate underlying the silicon dummy layer;

forming a first spacer and a second spacer on opposing sides of the silicon dummy layer;

removing the silicon dummy layer to form an opening, wherein a width of the opening between a top surface of the first spacer and a top surface of the second spacer is greater than a width of the opening between a bottom surface of the first spacer and a bottom surface of the second spacer; and

forming a gate electrode in the opening.

12. The method of claim 11, wherein a width of the gate electrode at a top surface of the gate electrode is greater than a width of the gate electrode at a bottom surface of the gate electrode.

13. The method of claim 11, comprising forming a gate dielectric in the opening prior to forming the gate electrode.

14. The method of claim 13, wherein a width of the gate dielectric at a top surface of the gate dielectric is greater than a width of the gate dielectric at a bottom surface of the gate dielectric.

15. The method of claim 13, comprising forming an interfacial layer in the opening prior to forming the gate dielectric, wherein a width of the interfacial layer at a top surface of the interfacial layer is greater than a width of the interfacial layer at a bottom surface of the interfacial layer.

16. A method of forming a semiconductor device, comprising:

forming a silicon dummy layer;

etching the silicon dummy layer, comprising;

performing a first etch to define a first non-tapered sidewall of the silicon dummy layer and a second non-tapered sidewall of the silicon dummy layer;

performing a second etch to taper the first non-tapered sidewall of the silicon dummy layer to define a first tapered sidewall of the silicon dummy layer and to taper the second non-tapered sidewall of the silicon dummy layer to define a second tapered sidewall of the silicon dummy layer; and

performing a third etch using a third etch process to etch through a third portion of the silicon dummy layer, wherein the third etch exposes a top surface of a substrate underlying the silicon dummy layer;

forming a first spacer adjacent the first tapered sidewall of the silicon dummy layer and forming a second spacer adjacent the second tapered sidewall of the silicon dummy layer;

removing the silicon dummy layer to form an opening; and

forming a gate electrode in the opening.

17. The method of claim 16, comprising forming an interfacial layer in the opening prior to forming the gate electrode.

18. The method of claim 17, comprising forming a gate dielectric in the opening and over the interfacial layer prior to forming the gate electrode.

19. The method of claim 18, wherein:

a first sidewall of the interfacial layer that interfaces with the first spacer is tapered, and

a first sidewall of the gate dielectric that interfaces with the first spacer is tapered.

20. The method of claim 17, wherein a first sidewall of the interfacial layer that interfaces with the first spacer is tapered.