Method of forming spacers for a gate of a transistor

• US 10,043,890 B2
• Filed: 09/16/2016
• Issued: 08/07/2018
• Est. Priority Date: 09/18/2015
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Pollet, Olivier, Posseme, Nicolas
• Primary Examiner(s): MUNOZ, ANDRES F
• Application Number:
  US15/267,624
• Publication Number:
  US 20170084720A1
• Time in Patent Office: 690 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A method is provided for forming spacers of a gate of a field effect transistor, the gate including flanks and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer covering the gate; after the step of forming, at least one step of modifying the dielectric layer by putting the dielectric layer into presence of a plasma creating a bombarding of light ions; and at least one step of removing the modified dielectric layer including a dry etching performed by putting the modified dielectric layer into presence of a gaseous mixture including at least one first component with a hydrofluoric acid base that transforms the modified dielectric layer into non-volatile residue, and removing the non-volatile residue via a wet clean performed after the dry etching or a thermal annealing of sublimation performed after or during the dry etching.

Claims

1. A method for forming spacers of a gate of a field effect transistor, with the gate comprising flanks and a top and being located above a layer made of a semiconductor material, the method comprising:

forming a dielectric layer covering the gate;

modifying the dielectric layer, after the forming, by putting the dielectric layer into a presence of a plasma comprising ions with a hydrogen base and/or ions with a helium base, and choosing conditions of the plasma, including an energy of the ions and an ion implantation dose, such that the modifying comprises implanting the ions by bombarding the dielectric layer with the ions in the plasma, the bombarding being anisotropic in a direction parallel to the flanks of the gate, which modifies at least portions of the dielectric layer that are located on the top of the gate and on sides of the gate and that are perpendicular to the flanks of the gate, and which retains unmodified portions of the dielectric layer covering the flanks of the gate or portions unmodified over an entire thickness thereof;

removing humidity from the modified dielectric layer at a temperature greater than an ambient temperature; and

removing the modified dielectric layer, after the step of removing the humidity, comprising;

selective etching of the modified dielectric layer relative to the layer made of the semiconductor material and relative to the unmodified portions of the dielectric layer, the selective etching comprising a dry etching at the ambient temperature when at atmospheric pressure, performed by putting the modified dielectric layer into a presence of a gaseous mixture comprising at least one first component having a hydrofluoric acid base, with the at least one first component transforming the modified dielectric layer into non-volatile residue, and

only after the dry etching, wet cleaning the non-volatile residue at the ambient temperature when at the atmospheric pressure, or, only after the dry etching, thermal annealing to sublimate the non-volatile residue.

2. The method according to claim 1,

wherein the gaseous mixture further comprises a second component, and

wherein parameters of the dry etching, including a gas ratio between the at least one first component and the second component, are provided such that the modified dielectric layer is selectively etched relative to the layer made of the semiconductor material and relative to the unmodified portions of the dielectric layer.

3. The method according to claim 2, wherein the at least one first component is generated by evaporation using a liquid source or using a pressurized bottle.

4. The method according to claim 1, wherein said modifying and said removing are carried out in a chemical reactor.

5. The method according to claim 4,

wherein the chemical reactor comprises an enclosure, and

wherein the modifying and the removing are carried out at the ambient temperature when at the atmospheric pressure, or are carried out at a temperature greater than the ambient temperature when at a pressure less than the atmospheric pressure.

6. The method according to claim 1, wherein the gaseous mixture comprises hydrofluoric acid (HF).

7. The method according to claim 1, wherein the gaseous mixture is free from proton acceptor groups.

8. The method according to claim 1, wherein the gaseous mixture comprises a second component having an inert gas base, chosen from nitrogen and/or argon.

9. The method according to claim 8, wherein a gas ratio between the at least one first component and the second component is between 1:

25 and 1;

1.

10. The method according to claim 1, wherein the dry etching is carried out under a temperature between 15°

C. and 80°

C., at a pressure between 40 Torr and 760 Torr, and for a duration of up to about two minutes.

11. The method according to claim 1, wherein the thermal annealing is carried out at a temperature between 200°

C. and 400°

C.

12. The method according to claim 11, wherein the thermal annealing is carried out at a low pressure between 10.10⁻

3 Torr and 2 Torr.

13. The method according to claim 11, wherein the thermal annealing is carried out for a time between 60 seconds and 600 seconds.

14. The method according to claim 1, wherein the wet clean is carried out with a deionized water base.

15. The method according to claim 1, further comprising, prior to the removing, vacuum thermal annealing at a temperature greater than 100°

C.

16. The method according to claim 1, wherein the dielectric layer is formed from at least one dielectric material of which a dielectric constant k is less than or equal to 7.

17. The method according to claim 1, wherein the dielectric layer is a layer of nitride.

18. The method according to claim 1, wherein the dielectric layer is a layer with a silicon (Si) base.

19. The method according to claim 1, wherein a material of the dielectric layer is taken from:

SiCO, SiC, SiCN, SiON, SiOCN, SiCBN, SiOCH, and SiO_x, where x is a positive integer.

20. The method according to claim 1,

wherein the semiconductor material is silicon, and

wherein the selective etching is carried out with silicon and/or with a layer of silicon oxide.

21. The method according to claim 1, further comprising forming a hard mask of at least one silicon oxide layer located on the gate, or forming a shallow trench isolation.

22. The method according to claim 1, wherein said modifying comprises modifying all of a thickness of the dielectric layer over all of surfaces parallel to a plane of a substrate on which the gate is disposed, and not modifying all of the thickness over all of surfaces perpendicular to the plane.

23. The method according to claim 1,

wherein the layer made of the semiconductor material is taken from silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and

wherein the ions are taken from helium and/or hydrogen and/or ammonia.

24. The method according to claim 1, wherein the ions are with the hydrogen base and a flow rate of the ions is between 10 sccm and 500 sccm.

25. The method according to claim 1, wherein the ions are with the helium base and a flow rate of the ions is between 50 sccm and 500 sccm.

26. The method according to claim 1, wherein the modifying is carried out with a polarization voltage ranging from 20V to 500V, at a pressure between 5 mTorr and 100 mTorr, and at a temperature between 10°

C. and 100°

C.

27. The method according to claim 1, wherein the modifying modifies the dielectric layer in a continuous manner from a surface of the dielectric layer and over a thickness between 1 nm and 30 nm.

28. The method according to claim 1, wherein the field effect transistor is of a FDSOI type or of a FinFET type.

29. A method for forming spacers of a gate of a field effect transistor, with the gate comprising flanks and a top and being located above a layer made of a semiconductor material, the method comprising:

forming a dielectric layer covering the gate;

modifying the dielectric layer, after the forming, by putting the dielectric layer into a presence of a plasma comprising ions with a hydrogen base and/or ions with a helium base, and choosing conditions of the plasma, including an energy of the ions and an ion implantation dose, such that the modifying comprises implanting the ions by bombarding the dielectric layer with the ions in the plasma, the bombarding being anisotropic in a direction parallel to the flanks of the gate, which modifies at least portions of the dielectric layer that are located on the top of the gate and on sides of the gate and that are perpendicular to the flanks of the gate, and which retains unmodified portions of the dielectric layer covering the flanks of the gate or portions unmodified over an entire thickness thereof;

pre-annealing the modified dielectric layer at a temperature greater than an ambient temperature to remove humidity from the modified dielectric layer; and

removing the modified dielectric layer, after the pre-annealing, comprising;

selective etching of the modified dielectric layer relative to the layer made of the semiconductor material and relative to the unmodified portions of the dielectric layer, the selective etching comprising a dry etching at the ambient temperature when at atmospheric pressure, performed by putting the modified dielectric layer into a presence of a gaseous mixture comprising at least one first component having a hydrofluoric acid base, with the at least one first component transforming the modified dielectric layer into non-volatile residue, and

only after the dry etching, wet cleaning the non-volatile residue at the ambient temperature when at the atmospheric pressure, or, only after the dry etching, thermal annealing to sublimate the non-volatile residue.