Apparatus and method for controlling asymmetric modular multilevel converter

• US 10,044,294 B2
• Filed: 12/02/2016
• Issued: 08/07/2018
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: Industry Academic Cooperation Foundation
• Original Assignee: Industry Academic Cooperation Foundation, Korea Electrotechnology Research Institute
• Inventors: Park, Jungwook, Lee, Soohyoung
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US15/367,700
• Publication Number:
  US 20170163171A1
• Time in Patent Office: 613 Days
• Field of Search: 363 40, 363 5601, 363 5602, 363 65, 363 71, 363 95, 363 98, 363131, 363132
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4835 comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters

Abstract

Disclosed is an apparatus and method for controlling an asymmetric modular multilevel converter which allow numerous levels to be expressed according to a combination of modules each using a different voltage, comprising: an asymmetric arm configured with a full bridge and a half bridge; and a control method of controlling each capacitor level of the full bridges and capacitor level of the remaining half bridges to be different from one another by a full bridge structure, wherein each module configuring the asymmetric arm uses a different voltage and an output voltage is expressed by a combination thereof.

Claims

1. An apparatus for controlling an asymmetric modular multilevel converter, comprising:

an asymmetric arm connected between a positive (+) input terminal and a negative (−

) input terminal of a DC bus voltage (V_DC) and including

N modules of full bridge converter, and

K modules of half bridge converter, wherein said N and K are constant number, respectively; and

a control method controlling each capacitor voltage of the N modules of full bridge converter and each capacitor voltage of the K modules of half bridge converter to be different from one another,

wherein each module configuring the asymmetric arm uses a different voltage and an output voltage is expressed by a combination thereof,

each of the K modules of half bridge converter is responsible for an equally divided voltage, and

a sum of capacitor voltages of the K modules of half bridge converter is always equal to the DC bus voltage (V_DC) when the asymmetric modular multilevel converter (AMMC) is in a normal state.

2. The apparatus of claim 1, wherein:

an upper arm and a lower arm of the asymmetric arm are connected in series between the positive (+) input terminal and the negative (−

) input terminal, and a V_AC output terminal is connected between the upper arm and the lower arm to configure a single-phase asymmetric modular multilevel converter; and

three single-phase asymmetric modular multilevel converters are connected by sharing the DC bus voltage (V_DC) to configure a three-phase asymmetric modular multilevel converter.

3. The apparatus of claim 1, wherein:

capacitor voltages of the N modules of full bridge converter are configured to be different in sequence by control; and

a capacitor voltage of a first module of the N modules of full bridge converter is ½

of the DC bus voltage, a capacitor voltage of a second module of the N modules of full bridge converter is ¼

of the DC bus voltage, and a capacitor voltage of a Nth module of the N modules of full bridge converter is 2⁻

N of the DC bus voltage.

4. The apparatus of claim 1, wherein:

when the asymmetric arm includes only one module of half bridge converter, two levels of the output voltage are implemented by the asymmetric arm, and

when the asymmetric arm includes K modules of half bridge converter, K+1 levels of the output voltage in total are implemented by the asymmetric arm; and

a capacitor voltage reference value of the N modules of full bridge converter is 1/K.

5. The apparatus of claim 1, wherein the N modules of full bridge converter and the K modules of half bridge converter implement a total of 2^N·

K+1 levels of the output voltage.

6. The apparatus of claim 1, wherein:

when the asymmetric arm includes one module of half bridge converter, a sum of capacitor voltages of the K modules of half bridge converter is equal to the DC bus voltage (V_DC)·

(1−

2<sup>−

N</sup>), and

when a fault occurs at a DC circuit, a fault current is blocked by a capacitor voltage of 1/(1−

2<sup>−

N</sup>) times of the sum of capacitor voltages in the normal state.

7. The apparatus of claim 1, further comprising an asymmetric cascaded H-bridge converter,

wherein the asymmetric cascaded H-bridge converter includes full bridge converters connected in series, and

the asymmetric cascaded H-bridge converter subdivides the output voltage into a single-level, a multi-level, and a multilevel converter (MMC) to output a modified output having over ten output voltage levels.

8. The apparatus of claim 7, wherein, when the output voltage has J levels, the modified output voltage of the asymmetric cascaded H-bridge converter has (J−

1)·

2^N+1 levels, wherein said J is constant number.

9. A method of controlling an asymmetric modular multilevel converter, the asymmetric modular multilevel converter comprising an asymmetric arm connected between a positive (+) input terminal and a negative (−

) input terminal of a DC bus voltage (V_DC) and including

N modules of full bridge converter, and

K modules of half bridge converter, wherein said N and K are constant number, respectively,

the method comprising;

each of the K modules of half bridge converter is responsible for an equally divided voltage;

a sum of capacitor voltages of the K modules of half bridge converter is always equal to the DC bus voltage (V_DC) when the asymmetric modular multilevel converter is in a normal state; and

capacitor voltages of the N modules of full bridge converter are configured to be different in sequence by control,

wherein an output voltage of the K modules of half bridge converter is within a range of the DC bus voltage, and each of the capacitor voltages of the K modules of half bridge converter is maintained at a level of 1/KV_DC.

10. The method of claim 9, wherein, when a current (i) flows into an arm which configures the asymmetric modular multilevel converter from the positive input terminal of the DC bus voltage (V_DC) a capacitor voltage (V_C) applied to a capacitor of an nth module of the N modules of full bridge converter is controlled such that (V_DC/2ⁿ−

V_Cn)*i>

0, wherein the V_Cn is a capacitor voltage of the nth module.

11. The method of claim 10, wherein when (V_DC/2ⁿ−

V_Cn)>

0, the capacitor voltage of the nth module is equal to or lower than an optimal level and requires charging, and

when i>

0, the nth module is controlled by a negative state (−

) to charge the capacitor of the nth module.

12. The method of claim 10, wherein, when (V_DC/2ⁿ−

V_Cn)<

0, the capacitor voltage of the nth module is equal to or higher than an optimal level and requires discharging, and

when i<

0, the nth module is controlled by a negative state (−

) to discharge the capacitor of the nth module.

13. The method of claim 10, wherein:

when (V_DC/2ⁿ−

V_Cn)=0, the nth module is controlled by a zero state (0) to maintain the capacitor voltage of the nth module without charging or is controlled to repeat a positive state (+) or a negative state (−

); and

when (V_DC/2ⁿ−

V_Cn)<

0 while i>

0 and (V_DC/2ⁿ−

V_Cn)>

0 while i<

0, the nth module is controlled by the positive state (+) to discharge or charge the capacitor of the nth module.

14. The method of claim 9, wherein:

an upper arm and a lower arm of the asymmetric arm are connected in series between the positive input terminal and the negative input terminal, and a V_AC output terminal is connected between the upper arm and the lower arm to configure the asymmetric modular multilevel converter;

modules of each arm are controlled such that a sum of voltages of the K modules of half bridge converter applied to each of the upper arm and the lower arm is V_DC; and

a half of a total number of the half bridge converter of the upper arm and the lower arm is always turned on or off.

15. The method of claim 14, wherein voltage control of the K modules of half bridge converter is performed such that a module having the lowest voltage is first charged and a module having the highest voltage is first discharged.