Injection locked phase locked loop

• US 10,044,359 B1
• Filed: 09/11/2017
• Issued: 08/07/2018
• Est. Priority Date: 02/03/2017
• Status: Active Grant

• Current Assignee: Seoul National University R&DB Foundation (Seoul National University), SK Hynix Inc.
• Original Assignee: Seoul National University R&DB Foundation (Seoul National University), SK Hynix Inc.
• Inventors: Kim, Sungwoo, Ko, Han-Gon, Kim, Suhwan, Jeong, Deog-Kyoon
• Primary Examiner(s): Hernandez, William
• Application Number:
  US15/701,333
• Publication Number:
  US 20180226979A1
• Time in Patent Office: 330 Days
• Field of Search: 327147, 327150, 327156, 327159
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/083 the reference signal being additionally directly applied to the generator
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An injection locked phase locked loop includes an injection locked oscillator configured to generate an oscillation signal according to an injection signal and to generate a replica signal by replicating the oscillation signal when the injection signal is deactivated; a phase controller configured to generate a phase control signal according to a phase error signal; and an error detector configured to generate the phase error signal by comparing a phase of the oscillation signal and a phase of the replica signal, and to control a phase difference between the oscillation signal and the replica signal according to the phase control signal.

Claims

1. An injection locked phase locked loop comprising:

an injection locked oscillator configured to generate an oscillation signal according to an injection signal and to generate a replica signal by replicating the oscillation signal when the injection signal is deactivated;

a phase controller configured to generate a phase control signal according to a phase error signal; and

an error detector configured to generate the phase error signal by comparing a phase of the oscillation signal and a phase of the replica signal, and to control a phase difference between the oscillation signal and the replica signal according to the phase control signal.

2. The injection locked phase locked loop of claim 1, further comprising an injection signal generator configured to generate the injection signal, the injection signal having a pulse synchronized with a rising edge of a reference clock signal.

3. The injection locked phase locked loop of claim 1, wherein the injection locked oscillator comprises:

a plurality of oscillation circuits each including first and second input terminals and first and second output terminals, the plurality of oscillation circuits including a first oscillation circuit configured to output the oscillation signal at the first output terminal according to the injection signal;

an injection signal input circuit configured to connect the first and second output terminals of the first oscillation circuit; and

a replica circuit configured to generate the replica signal, the replica circuit being connected in parallel to the first oscillation circuit.

4. The injection locked phase locked loop of claim 1, wherein the error detector comprises:

a signal delay circuit configured to generate a delayed oscillation signal and a delayed replica signal according to the phase control signal, the delayed oscillation signal being generated by delaying the oscillation signal by a first delay amount, the delayed replica signal being generated by delaying the replica signal by a second delay amount; and

a signal comparison circuit configured to generate a comparison signal by comparing a phase of the delayed oscillation signal and a phase of the delayed replica signal.

5. The injection locked phase locked loop of claim 4, wherein the signal delay circuit comprises a variable delay circuit configured to delay the oscillation signal by the first delay amount, the first delay amount varying according to the phase control signal.

6. The injection locked phase locked loop of claim 5, wherein the signal delay circuit further comprises a fixed delay circuit configured to delay the replica signal by the second delay amount.

7. The injection locked phase locked loop of claim 4, wherein the error detector further comprises a signal output circuit configured to output the phase error signal by latching the comparison signal.

8. The injection locked phase locked loop of claim 1, further comprising:

a frequency controller configured to generate a frequency control signal according to a frequency error signal,

wherein the injection locked oscillator adjusts a frequency of the oscillation signal according to the frequency control signal, and

wherein the error detector compares the phase of the oscillation signal and the phase of the replica signal when the injection signal is activated and generates the frequency error signal.

9. The injection locked phase locked loop of claim 8, wherein the error detector comprises:

a signal delay circuit configured to generate a delayed oscillation signal and a delayed replica signal according to the phase control signal, the delayed oscillation signal being generated by delaying the oscillation signal by a first delay amount, the delayed replica signal being generated by delaying the replica signal by a second delay amount;

a signal comparison circuit configured to generate a comparison signal by comparing a phase of the delayed oscillation signal and a phase of the delayed replica signal; and

a signal output circuit configured to output the phase error signal and the frequency error signal by latching the comparison signal.

10. The injection locked phase locked loop of claim 9, wherein the error detector further comprises an activation control circuit configured to control the signal delay circuit by generating an activation signal in response to the oscillation signal and a reference clock signal.

11. The injection locked phase locked loop of claim 10, wherein the activation signal has a first logic value in response to an edge of the reference clock signal and has a second logic value in response to a falling edge of the oscillation signal.

12. The injection locked phase locked loop of claim 11, wherein the signal delay circuit comprises a variable delay circuit comprising:

a NAND gate performing a logical NAND operation on the activation signal and the oscillation signal;

an inverter inverting an output signal of the NAND gate and generating the delayed oscillation signal; and

a variable delay circuit including a capacitance adjusting circuit, the capacitance adjusting circuit adjusting a capacitance value in response to the phase control signal and being coupled between an output of the NAND gate and a ground.

13. The injection locked phase locked loop of claim 11, wherein the signal delay circuit includes a fixed delay circuit comprising:

a NAND gate performing a logical NAND operation on the activation signal and the replica signal; and

an inverter inverting an output signal of the NAND gate and generating the delayed replica signal.

14. The injection locked phase locked loop of claim 9, wherein the signal output circuit comprises:

a first flip-flop configured to latch the comparison signal in response to an inverted version of a delayed reference clock signal; and

a second flip-flop configured to latch the comparison signal in response to the delayed reference clock signal.

15. The injection locked phase locked loop of claim 14, wherein the signal output circuit further comprises a third flip-flop configured to latch an output signal of the first flip-flop in response to the delayed reference clock signal.

16. The injection locked phase locked loop of claim 15, wherein the third flip-flop latches the output signal of the first flip-flop when the second flip-flop latches the comparison signal in response to a rising edge of the delayed reference clock signal.

17. The injection locked phase locked loop of claim 9, wherein the frequency controller comprises:

an accumulator configured to accumulate values according to a sampling clock signal, each of the values being obtained by performing an arithmetic operation on the frequency error signal with one or more coefficients; and

a modulator configured to modulate an output signal of the accumulator and to generate the frequency control signal.

18. The injection locked phase locked loop of claim 9, wherein the phase controller comprises:

an accumulator configured to accumulate values according to a sampling clock signal, each of the values being obtained by performing an arithmetic operation on the phase error signal with one or more coefficients; and

a modulator configured to modulate an output signal of the accumulator and to generate the phase control signal.

19. The injection locked phase locked loop of claim 8, further comprising:

a frequency divider configured to generate a divided signal by dividing a frequency of the oscillation signal;

a phase comparator configured to compare a phase of the divided signal and a phase of a reference clock signal; and

a path selector configured to select either an output signal of the phase comparator or the frequency error signal, and to provide the selected signal to the frequency controller.

20. The injection locked phase locked loop of claim 19, wherein the path selector selects the output signal of the phase comparator when an initialization completion signal has a first logic value and selects the frequency error signal when the initialization completion signal has a second logic value, the initialization completion signal indicating whether an initial phase locking operation has been completed or not.