Sigma delta analog to digital converter

• US 10,044,368 B2
• Filed: 09/26/2017
• Issued: 08/07/2018
• Est. Priority Date: 10/24/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kropfitsch, Michael, Rigo, Massimo
• Primary Examiner(s): Young, Brian
• Application Number:
  US15/716,252
• Publication Number:
  US 20180115321A1
• Time in Patent Office: 315 Days
• Field of Search: 341143, 341155
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path
• CPC Class Codes: H03M 3/464 Details of the digital/analogue conversion in the feedback path
• CPC Class Codes: H03M 3/496 Details of sampling arrangements or methods

Abstract

A sigma delta analog to digital converter for converting an analog input into a digital output comprises a reference path for receiving a reference voltage. The reference path comprises a digital to analog converter. The digital to analog converter comprises a reference voltage input for receiving the reference voltage, wherein the reference voltage input comprises two contacts and wherein each contact is a beginning of a voltage line of two voltage lines. The digital to analog converter comprises a plurality of switches and a plurality of capacitors. The switches of the plurality of switches are configured to connect the digital to analog converter in a sampling phase with the reference voltage and to disconnect the digital to analog converter in an integrating phase from the reference voltage.

Claims

1. A sigma delta analog to digital converter for converting an analog input into a digital output,

wherein the sigma delta analog to digital converter comprises a reference path for receiving a reference voltage,

wherein the reference path comprises a digital to analog converter,

wherein the digital to analog converter comprises a reference voltage input for receiving the reference voltage,

wherein the reference voltage input comprises two contacts,

wherein each contact is a beginning of a voltage line of two voltage lines,

wherein the digital to analog converter comprises a plurality of switches and a plurality of capacitors,

wherein the switches of the plurality of switches are configured to connect the digital to analog converter in a sampling phase with the reference voltage input and to disconnect the digital to analog converter in an integrating phase from the reference voltage input,

wherein the switches of the plurality of switches are configured to connect the capacitors of the plurality of capacitors with each other so that the connected capacitors have a total sampling capacity in the sampling phase and a total integrating capacity in the integrating phase, and

wherein the total sampling capacity differs from the total integrating capacity.

2. The sigma delta analog to digital converter of claim 1, wherein the switches of the plurality of switches and the capacitors of the plurality of capacitors are line symmetrical arranged along the voltage lines.

3. The sigma delta analog to digital converter of claim 1, wherein the total sampling capacity is greater than the total integrating capacity.

4. The sigma delta analog to digital converter of claim 1,

wherein the capacitors of the plurality of capacitors and the switches of the plurality of switches are such arranged that at least two capacitors are connected in series in at least one of the sampling phase and the integrating phase, and

wherein one capacitor of these at least two capacitors is connected with the two voltage lines and arranged between the two voltage lines.

5. The sigma delta analog to digital converter of claim 1, wherein the capacitors of the plurality of capacitors are such arranged that at least two capacitors are arranged in series along each of the two voltage lines and that at least one capacitor is connected with the two voltage lines and arranged between the two voltages lines and is connected to a connection between the at least two capacitors arranged in series along the two voltage lines.

6. The sigma delta analog to digital converter of claim 1, wherein the capacitors of the plurality of capacitors and the switches of the plurality of switches are such arranged that at least along one voltage line at least two capacitors are connected in parallel in the sampling phase and are connected in series or in anti-series in the integrating phase.

7. The sigma delta analog to digital converter of claim 6, wherein the two capacitors have different capacities.

8. The sigma delta analog to digital converter of claim 1, wherein switches of the plurality of switches are configured to connect capacitors of the plurality of capacitors with a common mode voltage.

9. The sigma delta analog to digital converter of claim 8, wherein the two voltage lines are connected with each other via the switches connecting capacitors with the common mode voltage.

10. A sigma delta analog to digital converter for converting an analog input into a digital output, the sigma delta analog to digital converter comprising:

a digital to analog converter that comprises a plurality of switches, a plurality of capacitors, and a reference voltage input for receiving a reference voltage, wherein switches of the plurality of switches are configured to;

connect the digital to analog converter in a sampling phase with the reference voltage input and disconnect the digital to analog converter in an integrating phase from the reference voltage input; and

connect capacitors of the plurality of capacitors with each other so that the connected capacitors have a total sampling capacity in the sampling phase and a total integrating capacity in the integrating phase, wherein the total sampling capacity differs from the total integrating capacity.

11. A sigma delta analog to digital converter for converting an analog input into a digital output, the sigma delta analog to digital converter comprising:

a digital to analog converter that comprises a plurality of switches, a plurality of capacitors, and a reference voltage input for receiving a reference voltage, wherein switches of the plurality of switches are configured to;

connect the digital to analog converter in a sampling phase with the reference voltage input and disconnect the digital to analog converter in an integrating phase from the reference voltage input; and

connect capacitors of the plurality of capacitors with each other so that the connected capacitors have a total sampling capacity in the sampling phase and a total integrating capacity in the integrating phase, wherein the total sampling capacity equals the total integrating capacity.