Contactless communication device with receiver input voltage stabilization

• US 10,044,389 B2
• Filed: 04/10/2015
• Issued: 08/07/2018
• Est. Priority Date: 04/11/2014
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Merlin, Erich, Kranabenter, Helmut, Mendel, Stefan, Pieber, Michael
• Primary Examiner(s): Lu, Zhiyu
• Application Number:
  US14/684,318
• Publication Number:
  US 20150295608A1
• Time in Patent Office: 1,215 Days
• Field of Search: None
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H04B 1/1036 with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters H04B1/123 takes precedence; filter circuits H03H
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H
• CPC Class Codes: H04W 72/0446 Resources in time domain, e.g. slots or frames

Abstract

There is described a contactless communication device. The device comprises (a) a receiver unit (110, 610) having an antenna input (RXn, Vmid, RXp) for connecting to an antenna, the receiver unit (110, 610) being adapted to couple with a transmitting device and to receive an RF signal transmitted by the transmitting device, the receiver unit (110, 610) being further adapted to determine a point of time relating to a position of data within the RF signal, (b) a comparator (120) adapted to generate a comparator output signal (agc_comp) which is indicative of a relation between a voltage at the antenna input (RXn, Vmid, RXp) of the receiver unit (110, 610) and a reference voltage (Vref), and (c) a voltage regulation circuit coupled to the comparator (120) and to the antenna input (RXn, Vmid, RXp) of the receiver unit (110, 610), the voltage regulation circuit being adapted to repetitively regulate the voltage at the antenna input (RXn, Vmid, RXp) based on the comparator output signal (agc_comp). The voltage regulation circuit is adapted to separate each repetitive regulation of the voltage at the antenna input (RXn, Vmid, RXp) by a first time constant prior to the point of time determined by the receiver unit (110, 610) and by a second time constant after the point of time determined by the receiver unit (110, 610), wherein the first time constant is smaller than the second time constant. There is also described a method, a computer program and a computer program product.

Claims

1. A contactless communication device, the device comprising:

a receiver unit having an antenna input for connecting to an antenna, the receiver unit being configured to couple with a transmitting device and to receive an RF signal transmitted by the transmitting device, and to provide to a clock signal derived from the RF signal, the receiver unit being further configured to determine a point of time relating to a position of data within the RF signal;

a programmable impedance circuit including a control terminal, opposing terminals, and a plurality of impedances, the plurality of impedances configured and arranged to respond to a comparator output signal presented at the control terminal by providing a selected impedance across the opposing terminals;

a comparator configured receive the derived clock signal and in response to generate the comparator output signal which is indicative of a relationship between a voltage at the antenna input of the receiver unit and a reference voltage including an indication of whether a peak voltage corresponding to the received RF signal is greater or less than the reference voltage, wherein the selected impedance across the opposing terminals is based on the comparator output signal;

a voltage regulation circuit coupled to the comparator and to the antenna input of the receiver unit, the voltage regulation circuit being configured to repetitively regulate the voltage at the antenna input in a control loop based on the comparator output signal and on a degree of gain sensitivity set by the selected impedance; and

wherein the voltage regulation circuit is configured to separate each repetitive regulation of the voltage at the antenna input by a variable time constant which depends on the point of time and to apply a first voltage regulation step size prior to the point of time determined by the receiver unit and a second voltage regulation step size after the point of time, wherein the control loop has a variable bandwidth that corresponds to the variable time constant, and each of the first voltage regulation step size and the second voltage regulation step size is defined based on the selected impedance.

2. The device according to claim 1, wherein the plurality of impedances is a plurality of resistors.

3. The device according claim 1, wherein the voltage regulation circuit includes a controller circuit configured to interconnect a number of the plurality of impedances such that said impedances are connected in parallel.

4. The device according to claim 1,

wherein the variable time constant includes a first time constant that equals a first factor divided by a predetermined frequency, and includes a

second time constant that equals a second factor divided by the predetermined frequency.

5. The device according to claim 1, wherein the receiver unit is configured to operate in a card-mode and to determine the point of time as the time where a reader-command is received from the transmitting device.

6. The device according to claim 1, wherein the receiver unit is configured to operate in a reader-mode and to determine the point of time as the time where a preamble is received or where a predefined time grid begins or where a predetermined minimal time before reception expires.

7. The device according to claim 1, wherein a second time constant is infinite.

8. The device according to claim 1, further comprising:

a signal processor coupled to the receiver unit and configured to process signals received by the receiver unit,

wherein the voltage regulation circuit is further configured to generate a signal processor control signal indicating that the signal processor is to be turned off for a predetermined period after each repetitive regulation of the voltage at the antenna input.

9. The device according claim 3, wherein the controller circuit is configured to interconnect the number of the plurality of impedances such that said impedances are connected in series.

10. The device according to claim 1, wherein the receiver unit is configured to determine the point of time by detecting particular RF signal content, and wherein a plurality of voltage regulation step sizes, including the first step size and the second step size, are defined relative to the point of time.

11. The device according to claim 1, wherein the receiver unit is configured to determine the point of time by adding a predetermined amount of time to a point of time where the RF signal is initially detected.

12. The device according to claim 1, wherein the comparator output signal indicates a number of impedances in a programmable impedance bank to be connected in parallel with each other and with the antenna input.

13. The device according to claim 1, wherein the receiver unit includes a differential receiver having a positive input terminal and a negative input terminal, and wherein the plurality of impendences includes a first impendence bank and a second impendence bank which are configured and arranged in series between the positive input terminal and the negative input terminal.

14. The device according to claim 1, further including a reference input terminal providing another reference voltage, wherein the receiver unit includes a differential receiver having a positive input terminal, a negative input terminal and a reference input terminal, and wherein the plurality of impendences includes a first impendence bank and a second impendence bank which are configured and arranged in series between the positive input terminal and the negative input terminal, and are electrically interconnected at the reference input terminal.