Methods and systems for skew tolerance in and advanced detectors for vector signaling codes for chip-to-chip communication

• US 10,044,452 B2
• Filed: 11/17/2017
• Issued: 08/07/2018
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Holden, Brian, Shokrollahi, Amin, Singh, Anant
• Primary Examiner(s): Wong, Linda
• Application Number:
  US15/816,941
• Publication Number:
  US 20180076912A1
• Time in Patent Office: 263 Days
• Field of Search: 375219, 375220, 375222, 375295, 375316, 375324, 375325, 375340, 375341
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: H04B 17/364 Delay profiles
• CPC Class Codes: H04B 3/00 Line transmission systems combined with near-field transmission systems H04B5/00
• CPC Class Codes: H04B 3/02 Details
• CPC Class Codes: H04B 5/26 using coils
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0643 block codes
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links
• CPC Class Codes: H04L 25/0268 with modulation and subsequent demodulation
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes
• CPC Class Codes: H04L 7/043 Pseudo-noise [PN] codes variable during transmission synchronisation of spread spectrum receivers H04B1/69
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.

Claims

1. A method comprising:

receiving a set of at least three input signals via a corresponding set of wires of a multi-wire bus, each input signal of the set of at least three input signals associated with a symbol of a codeword of at least a ternary vector signaling code;

generating, using a set of at least three transistor circuits, a set of at least three weighted input signals, each transistor circuit of the set of at least three transistor circuits receiving a corresponding input signal of the set of at least three input signals and responsively generating a corresponding weighted input signal of the set of at least three weighted input signals by applying a respective weight to the corresponding input signal; and

providing each weighted input signal of the set of at least three weighted input signals to a corresponding summing node of a pair of summing nodes and responsively generating a pair of summing-node levels, wherein at least one summing-node level of the pair of summing node levels corresponds to an analog summation of at least two weighted input signals of the set of at least three weighted input signals.

2. The method of claim 1, further comprising generating a comparison result by comparing the pair of summing-node levels on the pair of summing nodes.

3. The method of claim 2, wherein the comparison result corresponds to an output bit.

4. The method of claim 2, further comprising providing the comparison result to a decoder operating on a set of comparison results for generating a set of output bits.

5. The method of claim 1, wherein applying the respective weight comprises receiving the corresponding input signal at a transistor circuit of the set of at least three transistor circuits, the transistor circuit comprising an integer number of transistors connected in parallel, wherein the integer number corresponds to the respective weight.

6. The method of claim 1, wherein applying the respective weight comprises receiving the corresponding input signal at a transistor circuit of the set of at least three transistor circuits, the transistor circuit comprising a single transistor, and wherein the respective weight corresponds to one or more transistor characteristics of the single transistor.

7. The method of claim 6, wherein the one or more transistor characteristics comprises channel length.

8. The method of claim 6, wherein the one or more transistor characteristics comprises transfer current.

9. The method of claim 1, further comprising providing at least one offset signal to at least one of the pair of summing nodes.

10. The method of claim 1, wherein the pair of summing-node values correspond to a differential voltage output.

11. The method of claim 10, wherein the differential voltage output is generated by drawing a differential current based on the set of at least three weighed input signals through a differential pair of pull-up resistors connected to the pair of summing nodes.

12. The method of claim 1, wherein each of the set of at least three transistors applies an equal respective weight to the corresponding input signal.

13. The method of claim 1, wherein each of the set of at least three transistors applies a weight selected from a set of at least two distinct weightings as the respective weight.

14. The method of claim 1, wherein the vector signaling code is a permutation modulation (PM) code.

15. The method of claim 1, wherein the three or more input signals correspond to a portion of the symbols of the codeword of the vector signaling code.

16. The method of claim 1, wherein the three or more input signals correspond to all the symbols of the codeword of the vector signaling code.

17. The method of claim 1, wherein the set of at least three transistor circuits collectively comprises a balanced set of weights.

18. The method of claim 1, wherein the set of at least three weighted signals are weighted according to an input permutation of a set of input permutations for fully detecting the codeword of the vector signaling code.

19. The method of claim 1, further comprising selecting each input signal of the set of at least three input signals from respective locations in a storage buffer.

20. The method of claim 19, wherein each input signal of the set of at least three input signals is selected from the respective location according a measured skew.