Predictive memory maintenance

• US 10,048,877 B2
• Filed: 12/21/2015
• Issued: 08/14/2018
• Est. Priority Date: 12/21/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Miller, Shaun M., Mangold, Richard P.
• Primary Examiner(s): Bonzo, Bryce P
• Assistant Examiner(s): Arcos, Jeison C
• Application Number:
  US14/976,921
• Publication Number:
  US 20170177246A1
• Time in Patent Office: 967 Days
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Abstract

Predictive memory maintenance in accordance with one aspect of the present description, can anticipate a failure of a selected primary memory die of an array, and pre-load a spare memory die with the data of the selected primary memory die deemed to have a likelihood of failure, prior to any actual failure of the selected memory die. In the event that the selected primary memory die does subsequently fail, the spare memory die pre-loaded with the data of the selected primary memory die can readily take the place of the failed primary memory die with a pre-existing copy of the data of the failed primary memory die. Other aspects are described herein.

Claims

1. An apparatus for use with a memory having a plurality of dies including a spare memory die, comprising:

selection logic configured to determine memory performance of operational memory dies of a memory, and select an operational memory die of the memory for potential replacement as a function of memory die performance; and

data mirror logic configured to mirror to a spare memory die in anticipation of a potential failure and subsequent replacement of the selected operational memory die, data written to the selected operational memory die after the selected operational memory die was selected for potential replacement and prior to a potential failure and replacement of the selected operational memory die.

2. The apparatus of claim 1 further comprising:

die failure detection logic configured to detect failure of the selected operational memory die; and

die replacement logic configured to, in response detection of the failure of the selected operational memory die, disable the failed operational memory die and replace the failed operational memory die with the spare memory die wherein the spare memory die has data mirrored from the selected operational memory die prior to a detection of a failure of the selected operational memory die.

3. The apparatus of claim 1, further comprising:

error correction code logic configured to read data from the operational memory dies of the memory including the selected operational memory die, wherein the read data is encoded in accordance with an error correction code, the error correction code logic having decoder logic configured to decode the encoded read data, error detection logic configured to detect an error in the decoded read data, and error correction logic configured to attempt to correct a detected error in the decoded read data, wherein the error correction code logic is further configured to, in response to a failure by the error correction logic to correct a detected error in the decoded read data, read data from the spare memory die wherein the read data is encoded in accordance with an error correction code, and substitute the encoded read data from the spare memory die for the encoded read data from the selected operational memory die.

4. The apparatus of claim 3 wherein the decoder logic is further configured to decode the encoded read data which includes the encoded read data from the spare memory die, and wherein the error detection logic is further configured to detect an error in the decoded read data which includes the decoded read data from the spare memory die, and wherein the error correction logic is further configured to correct a detected error in the decoded read data which includes the decoded read data from the spare memory die.

5. The apparatus of claim 1 further comprising cyclical predictive memory maintenance logic configured to cyclically perform predictive maintenance of the memory in a plurality of maintenance cycles, wherein in each maintenance cycle, said selection logic is further configured to determine in each maintenance cycle, the memory performance of the operational memory dies of the memory, and to select an operational memory die of the memory for potential replacement as a function of the memory die performance;

and wherein said data mirror logic is further configured to in each maintenance cycle, mirror data for the selected operational memory die to the spare memory die.

6. The apparatus of claim 5 further comprising cyclical refresh logic configured to cyclically perform refreshing of the memory in a plurality of refresh cycles, wherein the predictive memory maintenance logic is further configured to perform each maintenance cycle in association with a refresh cycle.

7. The apparatus of claim 1 wherein said selection logic includes logic configured to determine memory performance of operational memory dies of the memory, including logic configured to accumulate over a period of time, comparative statistical performance data representing the comparative performance of each memory die of the memory with respect to a particular performance criteria, and logic configured to select an operational memory die of the memory for potential replacement as a function of the operational memory die having the worst comparative performance over the period of time.

8. The apparatus of claim 7 wherein the performance criteria includes raw bit error rate.

9. A system for use with a display, comprising:

a processor;

a video controller configured to control the display in response to the processor;

a memory configured to store data from the processor and having a plurality of memory dies including a spare memory die; and

a memory controller configured to control the memory, said memory controller including;

selection logic configured to determine memory performance of operational memory dies of the memory, and select an operational memory die of the memory for potential replacement as a function of memory die performance; and

data mirror logic configured to mirror to a spare memory die in anticipation of a potential failure and subsequent replacement of the selected operational memory die, data written to the selected operational memory die after the selected operational memory die was selected for potential replacement and prior to a potential failure and replacement of the selected operational memory die.

10. The system of claim 9 wherein the memory controller further includes:

die failure detection logic configured to detect failure of the selected operational memory die; and

die replacement logic configured to, in response detection of the failure of the selected operational memory die, disable the failed operational memory die and replace the failed operational memory die with the spare memory die wherein the spare memory die has data mirrored from the selected operational memory die prior to a detection of a failure of the selected operational memory die.

11. The system of claim 9, wherein the memory controller further includes:

error correction code logic configured to read data from the operational memory dies of the memory including the selected operational memory die, wherein the read data is encoded in accordance with an error correction code, the error correction code logic having decoder logic configured to decode the encoded read data, error detection logic configured to detect an error in the decoded read data, and error correction logic configured to attempt to correct a detected error in the decoded read data, wherein the error correction code logic is further configured to, in response to a failure by the error correction logic to correct a detected error in the decoded read data, read data from the spare memory die wherein the read data is encoded in accordance with an error correction code, and substitute the encoded read data from the spare memory die for the encoded read data from the selected operational memory die.

12. The system of claim 11 wherein the decoder logic is further configured to decode the encoded read data which includes the encoded read data from the spare memory die, and wherein the error detection logic is further configured to detect an error in the decoded read data which includes the decoded read data from the spare memory die, and wherein the error correction logic is further configured to correct a detected error in the decoded read data which includes the decoded read data from the spare memory die.

13. The system of claim 9 wherein the memory controller further includes cyclical predictive memory maintenance logic configured to cyclically perform predictive maintenance of the memory in a plurality of maintenance cycles, wherein in each maintenance cycle, said selection logic is further configured to determine in each maintenance cycle, the memory performance of the operational memory dies of the memory, and to select an operational memory die of the memory for potential replacement as a function of the memory die performance;

and wherein said data mirror logic is further configured to in each maintenance cycle, mirror data for the selected operational memory die to the spare memory die.

14. The system of claim 13 wherein the memory controller further includes refresh logic configured to cyclically performing refreshing of the memory in a plurality of refresh cycles, wherein the cyclical predictive memory maintenance logic is further configured to perform each maintenance cycle in association with a refresh cycle.

15. The system of claim 9 wherein said selection logic includes logic configured to determine memory performance of operational memory dies of the memory, including logic configured to accumulate over a period of time, comparative statistical performance data representing the comparative performance of each memory die of the memory with respect to a particular performance criteria, and logic configured to select an operational memory die of the memory for potential replacement as a function of the operational memory die having the worst comparative performance over the period of time.

16. The system of claim 15 wherein the performance criteria includes raw bit error rate.

17. A method, comprising:

determining memory performance of operational memory dies of a memory;

selecting an operational memory die of the memory for potential replacement as a function of memory die performance; and

mirroring to a spare memory die in anticipation of a potential failure and subsequent replacement of the selected operational memory die, data written to the selected operational memory die after the selected operational memory die was selected for potential replacement and prior to a potential failure and replacement of the selected operational memory die.

18. The method of claim 17 further comprising detecting a failure of the selected operational memory die, in response to detection of a failure of the selected operational memory die, disabling the failed operational memory die and replacing the failed operational memory die with the spare memory die wherein the spare memory die has data mirrored from the selected operational memory die prior to the detection of the failure of the selected operational memory die.

19. The method of claim 17, further comprising:

reading data from the operational memory dies of the memory including the selected operational memory die;

attempting error correction of the read data if the read data contains an error;

if the error correction is unsuccessful, modifying the read data by replacing read data read from the selected operational memory die with read data read from the spare memory die prior to detection of a failure of the selected operational memory die; and

attempting error correction of the modified read data if the modified read data contains an error.

20. The method of claim 17 further comprising cyclically performing maintenance of the memory in a plurality of maintenance cycles, each maintenance cycle including:

said determining memory performance of operational memory dies of the memory;

said selecting an operational memory die of the memory for potential replacement as a function of memory die performance; and

said mirroring data of the selected operational memory die to the spare memory die.

21. The method of claim 17 further comprising cyclically performing refreshing of the memory in a plurality of refresh cycles wherein each maintenance cycle is performed in association with a refresh cycle.

22. The method of claim 17 wherein said determining memory performance of operational memory dies of the memory includes accumulating over a period of time, comparative statistical performance data representing the comparative performance of each memory die of the memory with respect to a particular performance criteria, and wherein said selecting an operational memory die of the memory for potential replacement as a function of memory die performance includes selecting the operational memory die having the worst comparative performance over the period of time.

23. The method of claim 22 wherein the performance criteria includes raw bit error rate.