Methods and apparatus for memory tier page cache with zero file

• US 10,049,046 B1
• Filed: 09/30/2014
• Issued: 08/14/2018
• Est. Priority Date: 05/28/2014
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Inventors: Michaud, Adrian, Clark, Roy E., Taylor, Kenneth J.
• Primary Examiner(s): Lo, Ann J
• Assistant Examiner(s): Khan, Masud
• Application Number:
  US14/501,112
• Time in Patent Office: 1,414 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 16/00 Information retrieval; Database structures therefor; File system structures therefor
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/604 Details relating to cache allocation
• CPC Class Codes: G06F 2212/6046 Using a specific cache allocation policy other than replacement policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/653 Page colouring
• CPC Class Codes: G06F 2212/657 : Virtual address space management
• CPC Class Codes: G06F 2212/7201 : Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0655 : Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/067 : Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/40607 : Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Methods and apparatus for providing region zero-fill on demand for tiered memory including a first region in a first memory tier having a page cache in physical memory, where virtual memory includes a mmap of the first region. An input can be controlled between zeroes and the first region to the page cache.

Claims

1. A method, comprising:

providing zero-fill on demand for tiered memory including a first region in a first memory tier having a page cache in physical memory, wherein virtual memory includes a mmap of the first region, wherein the mmap for the first region is mapped to the virtual memory for a process, and wherein the tiered memory includes a second region that shares the page cache with the first region;

controlling an input between zeroes and the first region to the page cache; and

providing an attribute for the first region which when set on the first access to the page cache suppresses data transfer from the tiered memory to enable the zero-fill of the page cache.

2. The method according to claim 1, further including providing a multiplexer having an output coupled to the page cache and input coupled to the first region and a zero fill module.

3. The method according to claim 1, further including controlling a per region attribute to selectively suppress data transfer from the storage to the page cache.

4. The method according to claim 1, wherein the physical memory comprises SCM storage.

5. The method according to claim 1, wherein the page cache comprises DRAM memory.

6. An article, comprising:

a non-volatile computer-readable storage medium having stored instructions that enable a machine to;

provide region zero-fill on demand for tiered memory including a first region in a first memory tier having a page cache in physical memory, where virtual memory includes a mmap of the first region, wherein the mmap for the first region is mapped to the virtual memory for a process, and wherein the tiered memory includes a second region that shares the page cache with the first region;

control an input between zeroes and the first region to the page cache; and

control an attribute for the first region which when set on the first access to the page cache suppresses data transfer from the tiered memory to enable the zero-fill of the page cache.

7. The article according to claim 6, further including instructions to control a multiplexer having an output coupled to the page cache and input coupled to the first region and a zero fill module.

8. The article according to claim 6, further including instructions to control a per region attribute to selectively suppress data transfer from the storage to the page cache.

9. The article according to claim 6, wherein the physical memory comprises SCM storage.

10. The article according to claim 6, wherein the page cache comprises DRAM memory.

11. A system, comprising:

a memory; and

a processor coupled to the memory, the processor and the memory configured to;

provide region zero-fill on demand for tiered memory including a first region in a first memory tier having a page cache in physical memory, wherein virtual memory includes a mmap of the first region, wherein the mmap for the first region is mapped to the virtual memory for a process, and wherein the tiered memory includes a second region that shares the page cache with the first region;

control an input between zeroes and the first region to the page cache; and

control an attribute for the first region which when set on the first access to the page cache suppresses data transfer from the tiered memory to enable the zero-fill of the page cache.

12. The system according to claim 11, wherein the processor and the memory are further configured to control a multiplexer having an output coupled to the page cache and input coupled to the first region and a zero fill module.

13. The system according to claim 11, wherein the processor and the memory are further configured to control a per region attribute to selectively suppress data transfer from the storage to the page cache.

14. The system according to claim 11, wherein the physical memory comprises SCM storage.

15. The system according to claim 11, wherein the page cache comprises DRAM memory.