Multibit NAND media using pseudo-SLC caching technique

• US 10,049,047 B1
• Filed: 03/10/2017
• Issued: 08/14/2018
• Est. Priority Date: 03/10/2017
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kotte, Narasimhulu Dharani, Thamgaraj, Senthil, Reed, Robert, Kondo, Hitoshi
• Primary Examiner(s): Thammavong, Prasith
• Assistant Examiner(s): Blust, Jason W
• Application Number:
  US15/456,375
• Time in Patent Office: 522 Days
• Field of Search: None
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. The SSD further includes one or more volatile memory devices communicatively coupled to the memory controller, where at least one of the one or more volatile memory devices has a read cache area. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC write cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area.

Claims

1. A solid state drive (SSD) comprising:

a memory controller;

a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to the memory controller;

one or more volatile memory devices communicatively coupled to the memory controller, at least one of the one or more volatile memory devices having a read cache area; and

a host interface communicatively coupled to the memory controller, wherein

a first portion of the plurality of multibit NAND media devices is configured to operate as a pseudo-single-level cell (pSLC) write cache,

a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area, and

the memory controller is configured to;

write data received via the host interface to one or more blocks of the pSLC write cache,

transfer data from the one or more blocks of the pSLC write cache to one or more blocks of the multibit NAND media storage area,

read the data transferred to the multibit NAND media storage area and determine if an error correction code (ECC) error correction threshold has been exceeded for the data read, and

when the data read has been determined to exceed the ECC error correction threshold, write such data to one or more blocks of the read cache area when it is not full, and write such data to the pSLC write cache when the read cache area is full.

2. The SSD of claim 1, wherein a storage capacity of the pSLC write cache is equal to a result of multiplying a specified number of drive writes per day (N-DWPD) of the multibit NAND media devices, a specified number of years of operation of the multibit NAND media devices, 365 days, and a specified user data storage capacity, and dividing the result by a specified number of program/erase (PE) cycles of a block of the multibit NAND media devices.

3. The SSD of claim 2, wherein the memory controller is configured to write data contained in the one or more blocks of the pSLC write cache to the multibit NAND media storage area after a write threshold of the pSLC write cache has been exceeded.

4. The SSD of claim 3, wherein the write threshold of the pSLC write cache is determined by a storage capacity of the pSLC write cache divided by a fill ratio, which is a speed of the host interface divided by a write speed of the multibit NAND media devices configured to operate as the pSLC write cache.

5. The SSD of claim 1, wherein the memory controller is further configured to sequentially write the data contained in the one or more blocks of the pSLC write cache to one or more blocks of the multibit NAND media storage area.

6. The SSD of claim 5, wherein the memory controller performs an in-memory sorting within the one or more volatile memory devices of at least one of a set of logical block addresses (LBAs) and a set of logical cluster addresses (LCAs) corresponding to the data contained in the one or more blocks of the pSLC write cache to be written to one or more blocks of the multibit NAND media storage area.

7. The SSD of claim 1, wherein the memory controller is further configured to

mark blocks of the multibit NAND media storage area exceeding the ECC error correction threshold as bad blocks, and

write data to the bad blocks only when all other blocks of the multibit NAND media storage area that have not been marked as bad blocks have been occupied with data.

8. The SSD of claim 1, wherein the memory controller is further configured to collect host read statistics for each of the one or more blocks of the read cache area and multibit NAND media storage area.

9. The SSD of claim 8, wherein the memory controller is further configured to perform an eviction process when the read cache area is full, the eviction process comprising

the memory controller identifies one or more blocks of the multibit NAND media storage area that have a greater number of host reads than one or more blocks of the read cache area, and

the memory controller swaps data contained in the one or more blocks of the multibit NAND media storage area having the greater number of host reads with data contained in the one or more blocks of the read cache area having a fewer number of host reads.

10. The SSD of claim 1, wherein the plurality of multibit NAND media devices are multi-level cell (MLC) NAND media devices, triple-level cell (TLC) NAND media devices, or quad-level cell (QLC) NAND media devices.

11. A method of caching data in an solid state drive (SSD) having a plurality of multibit NAND media devices, the method comprising:

configuring a first portion of the plurality of multibit NAND media devices to operate as a pseudo-single-level cell (pSLC) write cache;

configuring a second portion of the plurality of multibit NAND media devices to operate as a multibit NAND storage area;

configuring a region of a volatile memory device communicatively coupled to the plurality of multibit NAND media devices as a read cache area;

receiving data from a host device connected to the SSD;

writing the data to one or more blocks of the pSLC write cache;

transferring data from the one or more blocks of the pSLC write cache to one or more blocks of the multibit NAND media storage area;

reading the data transferred to the multibit NAND media storage area;

determining if an error correction code (ECC) error correction threshold has been exceeded for the data read; and

for the data read exceeding the ECC error correction threshold, writing such data to one or more blocks of the read cache area when it is not full, and writing such data to the pSLC write cache when the read cache area is full.

12. The method of claim 11, wherein the step of configuring the portion of the plurality of multibit NAND media devices to operate as the pSLC write cache includes calculating a storage capacity of the pSLC write cache, wherein

the storage capacity of the pSLC write cache is equal to a result of multiplying a specified number of drive writes per day (N-DWPD) of the multibit NAND media devices, a specified number of years of operation of the multibit NAND media devices, 365 days, and a specified user data storage capacity, and dividing the result by a specified number of program/erase (PE) cycles of a block of the multibit NAND media devices.

13. The method of claim 12, further comprising:

writing data contained in the one or more blocks of the pSLC write cache to the multibit NAND media storage area after a write threshold of the pSLC write cache has been exceeded.

14. The method of claim 13, wherein the write threshold is a storage capacity of the pSLC write cache divided by a fill ratio, which is a speed of the host interface divided by a write speed of the multibit NAND media configured to operate as the pSLC write cache.

15. The method of claim 11, further comprising:

sequentially writing the data contained in the one or more blocks of the pSLC write cache to one or more blocks of the multibit NAND media storage area.

16. The method of claim 15, wherein the step of sequentially writing the data contained in the one or more blocks of the pSLC write cache to the one or more blocks of the multibit NAND media storage area includes sorting, in the volatile memory communicatively coupled to the plurality of multibit NAND media devices, at least one of a set of logical block addresses (LBAs) and a set of logical cluster addresses (LCAs) corresponding to the data contained in the one or more blocks of the pSLC write cache before writing the data to one or more blocks of the multibit NAND media storage area.

17. The method of claim 11, further comprising:

marking blocks of the multibit NAND media storage area exceeding the ECC error correction threshold as bad blocks, and

writing data to the bad blocks when all other blocks of the multibit NAND media storage area that have not been marked as bad blocks have been occupied with data.

18. The method of claim 12, further comprising:

collecting host read statistics for each one of the one or more blocks of the read cache area and the multibit NAND media storage area.

19. The method of claim 18, further comprising:

performing an eviction process when the read cache area is full, the eviction process comprising;

identifying one or more blocks of the multibit NAND media storage area that have a greater number of host reads than one or more blocks of the read cache area, and

swapping data contained in the one or more blocks of the multibit NAND media storage area having the greater number of host reads with data contained in the one or more blocks of the read cache area having a fewer number of host reads.

20. The method of claim 11, wherein the plurality of NAND media devices are multi-level cell (MLC) NAND media devices, triple-level cell (TLC) NAND media devices, or quad-level cell (QLC) NAND media devices.