Chip package and fabrication method thereof
First Claim
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1. A chip package, comprising:
- a substrate having a first surface and a second surface opposite to the first surface;
a capacitive sensing layer disposed below the first surface and having a third surface opposite to the first surface, the capacitive sensing layer comprising;
a plurality of capacitive sensing electrodes disposed on the third surface, anda plurality of metal wires disposed on the capacitive sensing electrodesa computing chip disposed above the capacitive sensing layer and electrically connected to the capacitive sensing electrodes; and
a recess extending from the second surface to the first surface to expose the metal wires, and the computing chip is in the recess.
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Abstract
A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.
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Citations
20 Claims
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1. A chip package, comprising:
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a substrate having a first surface and a second surface opposite to the first surface; a capacitive sensing layer disposed below the first surface and having a third surface opposite to the first surface, the capacitive sensing layer comprising; a plurality of capacitive sensing electrodes disposed on the third surface, and a plurality of metal wires disposed on the capacitive sensing electrodes a computing chip disposed above the capacitive sensing layer and electrically connected to the capacitive sensing electrodes; and a recess extending from the second surface to the first surface to expose the metal wires, and the computing chip is in the recess. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of fabricating a chip package, comprising:
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receiving a substrate having a first surface and a second surface opposite to the first surface; forming a capacitive sensing layer below the first surface, and the capacitive sensing layer having a third surface opposite to the first surface, the capacitive sensing layer being formed by; forming a plurality of metal wires below the first surface; and forming a plurality of capacitive sensing electrodes below the metal wires; forming a computing chip above the capacitive sensing layer to electrically connect the capacitive sensing electrodes and the computing chip; and forming a recess extending from the second surface to the first surface to expose the metal wires, and the computing chip being formed in the recess. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification