Refresh request queuing circuitry

• US 10,049,716 B2
• Filed: 08/19/2015
• Issued: 08/14/2018
• Est. Priority Date: 02/13/1999
• Status: Expired due to Fees

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US14/830,667
• Publication Number:
  US 20160180920A1
• Time in Patent Office: 1,091 Days
• Field of Search: 711106
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of queued pending refresh requests for a memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and second circuitry to set a refresh flag in response to a determination that the number of queued pending refresh requests exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.

Claims

1. A method, comprising:

incrementing a first refresh request count in response to receiving a refresh request for a first memory bank, wherein the first refresh address count increments for each refresh operation;

comparing the first refresh request count to a first refresh address count and outputting a first pending refresh signal if the first refresh request count and the first refresh address count differ; and

issuing a refresh command to complete a refresh of the first memory bank during one clock cycle in response to the first pending refresh signal.

2. The method of claim 1, further comprising issuing the refresh command on a clock cycle when the first memory bank is not busy with an access operation.

3. The method of claim 1, wherein said incrementing a first refresh request count occurs periodically.

4. The method of claim 3, further comprising:

incrementing a second refresh request count in response to receiving a refresh request for a second memory bank; and

comparing the second refresh request count to a second refresh address count and outputting a second pending refresh signal if the second refresh request count and the second refresh address count differ.

7. The method of claim 4, wherein said incrementing a second refresh request count occurs periodically.

8. The method of claim 1, wherein the first refresh request count is periodically incremented according to a predetermined number of clock cycles.

5. The method of 4, further comprising issuing a refresh command to the second memory bank in response to the second pending refresh signal.

6. The method of 5, further comprising issuing the second refresh command to the second memory bank on a clock cycle when the second memory bank is not busy with an access operation.

9. An apparatus, comprising:

a plurality of counters; and

circuitry configured to;

change a count of a first counter from the plurality of counters for each refresh request for a memory bank, wherein the change of the count of the first counter comprises an increment of the count of the first counter;

change a count of a second counter from the plurality of counters for each refresh operation for the memory bank, wherein the change of the count of the second counter comprises an increment of the count of the second counter;

compare a current value of the first counter to a current value of the second counter and output a pending refresh signal for the memory bank if the values differ; and

issue a refresh command to perform a single clock cycle refresh of the memory bank in response to the pending refresh signal.

10. The apparatus of claim 9, wherein the circuitry is further configured to issue the refresh command on a clock cycle if the memory bank is not busy with an access operation.

11. The apparatus of claim 9, wherein the memory bank comprises a first memory bank, and wherein the circuitry is further configured to:

change a count of a third counter from the plurality of counters for each refresh request for a second memory bank;

change a count of a fourth counter from the plurality of counters for each refresh operation for the second memory bank; and

compare a current value of the third counter to a current value of the fourth counter and output a pending refresh signal for the second memory bank if the values differ.

12. The apparatus of claim 11, wherein the circuitry is further configured to issue a refresh command to perform a single clock cycle refresh of the second memory bank in response to the pending refresh signal for the second memory bank.