×

Contention-free dynamic logic

  • US 10,049,726 B1
  • Filed: 02/03/2017
  • Issued: 08/14/2018
  • Est. Priority Date: 02/03/2017
  • Status: Active Grant
First Claim
Patent Images

1. A method comprising:

  • pre-charging a global bit line responsive to assertion of a global bit line pre-charge signal;

    decoding a read address at a decoder circuit;

    pre-charging a first local bit line responsive to a first local bit line pre-charge signal supplied from the decoder circuit;

    pre-charging a second local bit line responsive to a second local bit line pre-charge signal supplied from the decoder circuit;

    activating a first global keeper transistor coupled between a voltage supply node and the global bit line responsive to the first local bit line pre-charge signal or the second local bit line pre-charge signal being deasserted;

    activating a pull-down transistor coupled between the global bit line and a ground node responsive to a global pull-down signal being asserted, the global pull-down signal being asserted responsive to the first local bit line being at a first value or the second local bit line being at the first value; and

    supplying the global pull-down signal to a first gate of a first local bit line keeper transistor of a first local bit line keeper circuit coupled between the voltage supply node and the first local bit line.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×