Contention-free dynamic logic

• US 10,049,726 B1
• Filed: 02/03/2017
• Issued: 08/14/2018
• Est. Priority Date: 02/03/2017
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schaefer, Alexander W., McIntyre, David H.
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US15/424,367
• Publication Number:
  US 20180226122A1
• Time in Patent Office: 557 Days
• Field of Search: 36518511, 365 51, 365 63, 36518902, 36523002, 36523006
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The dynamic NOR circuit includes a first keeper circuit having a first keeper transistor and a second keeper transistor serially coupled between the first voltage supply node and the dynamic node. The dynamic NOR circuit includes a first pull down circuit coupled between the dynamic node and ground. A first input signal is coupled to a gate of a first pull-down transistor in the first pull-down circuit and is also coupled to a gate of the first keeper transistor. A first keeper enable signal is coupled to a gate of the second keeper transistor. Additional keeper circuits and pull down circuits coupled to the dynamic node allow the dynamic NOR structure to handle a plurality of input signals.

Claims

1. A method comprising:

pre-charging a global bit line responsive to assertion of a global bit line pre-charge signal;

decoding a read address at a decoder circuit;

pre-charging a first local bit line responsive to a first local bit line pre-charge signal supplied from the decoder circuit;

pre-charging a second local bit line responsive to a second local bit line pre-charge signal supplied from the decoder circuit;

activating a first global keeper transistor coupled between a voltage supply node and the global bit line responsive to the first local bit line pre-charge signal or the second local bit line pre-charge signal being deasserted;

activating a pull-down transistor coupled between the global bit line and a ground node responsive to a global pull-down signal being asserted, the global pull-down signal being asserted responsive to the first local bit line being at a first value or the second local bit line being at the first value; and

supplying the global pull-down signal to a first gate of a first local bit line keeper transistor of a first local bit line keeper circuit coupled between the voltage supply node and the first local bit line.

2. The method as recited in claim 1 further comprising:

turning off a second global keeper transistor serially coupled with the first global keeper transistor between the voltage supply node and the global bit line responsive to the first local bit line being at the first value or the second local bit line being at the first value.

3. The method as recited in claim 1 further comprising:

supplying a plurality of N read word lines from the decoder circuit to a first group of memory cells, N being an integer;

giving the first local bit line a value based on a first memory cell associated with one of the N read word lines; and

activating the first global keeper transistor responsive to the first local bit line pre-charge signal being deasserted.

4. The method as recited in claim 1 further comprising:

supplying a second plurality of N read word lines from the decoder circuit to a second plurality of memory cells;

giving the second local bit line a value based on a second memory cell associated with one of the second plurality of N read word lines; and

activating the first global keeper transistor responsive to the second local bit line pre-charge signal being deasserted.

5. The method as recited in claim 1 further comprising:

pre-charging a third local bit line responsive to a third local bit line pre-charge signal supplied from the decoder circuit;

pre-charging a fourth local bit line responsive to a fourth local bit line pre-charge signal supplied from the decoder circuit;

activating a second global keeper transistor responsive to the third local bit line pre-charge signal or the fourth local bit line pre-charge signal being deasserted.

16. The method as recited in claim 1 further comprising:

supplying to a second gate of a second local bit line keeper transistor of the first local bit line keeper circuit a first local bit line keeper enable signal from the decoder circuit.

17. The method as recited in claim 16 further comprising:

supplying a third gate of a third local bit line keeper transistor of a second local bit line keeper circuit coupled between the voltage supply node and the second local bit line with the global pull-down signal; and

supplying a fourth gate of a fourth local bit line keeper transistor of the second local bit line keeper circuit with a second local bit line keeper enable signal from the decoder circuit.

6. An apparatus comprising:

a first pre-charge transistor coupled between a voltage supply node and a global bit line;

a first global keeper circuit including a first keeper transistor and a second keeper transistor coupled between the voltage supply node and the global bit line;

a second pre-charge transistor coupled between the voltage supply node and a first local bit line;

a third pre-charge transistor coupled between the voltage supply node and a second local bit line;

a first global pull-down circuit coupled to receive a first global pull-down signal, the first global pull-down circuit including a pull-down transistor coupled between the global bit line and a ground node; and

a first global keeper enable signal coupled to a gate of the first keeper transistor, the first global keeper enable signal being a logical combination of a second pre-charge control signal coupled to a gate of the second pre-charge transistor and a third pre-charge control signal coupled to a gate of the third pre-charge transistor; and

a first local bit line keeper circuit including a third keeper transistor coupled between the voltage supply node and the first local bit line, wherein a gate of the third keeper transistor is coupled to the first global pull-down signal.

7. The apparatus as recited in claim 6, wherein a first logic circuit logically combines a first local bit line and a second local bit line to generate the first global pull-down signal and is coupled to activate the second keeper transistor according to a first value of the first global pull-down signal and to turn off the pull-down transistor responsive to the first value of the first global pull-down signal.

8. The apparatus as recited in claim 6, further comprising:

a second logic circuit to logically combine the second pre-charge control signal and the third pre-charge control signal and provide the first global keeper enable signal.

9. The apparatus as recited in claim 6, further comprising:

a decoder circuit coupled to receive a read address and supply the second pre-charge control signal and the third pre-charge control signal.

10. The apparatus as recited in claim 9, further comprising:

a second local bit line keeper circuit including a fifth keeper transistor and a sixth keeper transistor coupled between the voltage supply node and the second local bit line, the fifth keeper transistor coupled to receive the first global pull-down signal.

11. The apparatus as recited in claim 10, further comprising:

a fourth keeper transistor coupled in series with the third keeper transistor between the voltage supply node and the first local bit line;

wherein the decoder circuit is coupled to supply a first local bit line keeper enable signal to the fourth keeper transistor and the decoder circuit is coupled to supply a second local bit line keeper enable signal to the sixth keeper transistor.

12. The apparatus as recited in claim 9, further comprising:

first plurality of read ports coupled to receive a first plurality of read word lines from the decoder circuit and coupled to supply the first local bit line; and

a second plurality of read ports coupled to receive a second plurality of read word lines from the decoder circuit and coupled to supply the second local bit line.

13. The apparatus as recited in claim 6 further comprising:

a second global keeper circuit including a fifth keeper transistor and a sixth keeper transistor coupled between the voltage supply node and the global bit line;

a second global pull-down circuit including a second pull-down transistor coupled between the global bit line and the ground node.

14. The apparatus as recited in claim 6 wherein a value of the global bit line is determined according to a value of a plurality of local bit lines including the first and second local bit line.

15. The apparatus as recited in claim 11 wherein the decoder circuit delays activation of the fourth keeper transistor according to a frequency of a clock signal.

18. The apparatus as recited in claim 9 further comprising:

a fourth keeper transistor coupled in series with the third keeper transistor between the voltage supply node and the first local bit line; and

wherein the decoder circuit is coupled to supply a first local bit line keeper enable signal to the fourth keeper transistor.