Non-volatile memory with floating gate having protruding portion

• US 10,049,741 B2
• Filed: 02/19/2017
• Issued: 08/14/2018
• Est. Priority Date: 07/27/2016
• Status: Active Grant

• Current Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Tailliet, Francois
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US15/436,829
• Publication Number:
  US 20180033487A1
• Time in Patent Office: 541 Days
• Field of Search: 365 63, 36518529, 36518522, 36518517, 36518518
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region

Abstract

A memory cell includes a source region and a drain region disposed in a semiconductor body. A channel region is disposed in the semiconductor body between the source region and the drain region. A floating gate is disposed between the semiconductor body and the control gate. The floating gate includes a protruding portion that is located over the channel region between the source and drain regions and spaced therefrom. The protruding portion is separated from the channel region by a first insulating layer that is thinner than a second insulating layer that separates remaining portions of the floating gate from the channel region.

Claims

1. An electrically erasable and programmable nonvolatile memory device comprising a memory cell, the memory cell comprising:

a source region disposed in a semiconductor body;

a drain region disposed in the semiconductor body;

a channel region disposed in the semiconductor body between the source region and the drain region;

a control gate; and

a floating gate disposed between the semiconductor body and the control gate, wherein the floating gate includes a protruding portion that is located over the channel region between the source and drain regions and spaced therefrom, the protruding portion being separated from the channel region by a first insulating layer that is thinner than a second insulating layer that separates remaining portions of the floating gate from the channel region, and wherein the control gate includes a lateral portion that extends beyond lateral ends of the floating gate and is vertically aligned with a portion of the channel region.

2. The device according to claim 1, wherein the protruding portion is substantially centered in the middle of the channel region and is laterally insulated from the source and drain regions by the second insulating layer.

3. The device according to claim 1, wherein the memory device comprises:

a memory plane that includes the memory cell and a plurality of additional memory cells arranged in a matrix array of rows and columns, the rows being divided into memory words of a plurality of memory cells; and

an erase circuit that is configured to erase a memory word by way of a collective erasing operation that turns on all the memory cells of the memory word.

4. The device according to claim 3, wherein the additional memory cells each have the same structure as the memory cell and wherein the erase circuit is configured to apply a negative erasing pulse to the control gates of the of the memory cells of the memory word and a zero voltage to the channel region of the memory cells of the memory word.

5. The device according to claim 3, wherein the memory device further comprises a programming circuit configured to program the memory word by applying a programming pulse to the control gates of all the memory cells of the memory word, while inhibiting the programming of those memory cells of the memory word that is not to be programmed.

6. The device according to claim 5, wherein the programming circuit is configured to apply, by way of programming pulse, a positive voltage that is sufficient to invert the channel regions of the memory cells, to apply a zero voltage to the channel regions of the memory cells to be programmed, and to apply an inhibiting voltage that is positive and lower than the positive voltage via the drain region of the memory cells that are not to be programmed.

7. The device according to claim 1, wherein the memory cell includes a selection structure configured to electrically isolate from, or connect to, a source line of the memory device that is associated with the source region of the memory cell.

8. The device according to claim 7, wherein the selection structure comprises the lateral portion of the control gate.

9. The device according to claim 8, further comprising:

a memory plane that includes the memory cell and a plurality of additional memory cells arranged in a matrix array of rows and columns, wherein

the additional memory cells each have the same structure as the memory cell, the memory plane including two connected memory cells to which a logic datum can be written,

the source regions of the two connected memory cells are electrically connected to each other by a source metal track,

the drain regions of the memory cells are electrically connected to each other by a drain metal track,

the source line comprises a metal track extending in a direction of the columns of the memory plane over one of two connected memory cells,

the source line is connected, above the source region of the one of two connected memory cells, by a via to the source metal track, and

a bit line comprising a metal track extends in the direction of the columns of the memory plane above the other of the two connected memory cells and is connected, above the drain region of the other of the two connected memory cells, by a via to the drain metal track.

10. The device according to claim 1, wherein the memory cell further comprises:

a third insulating layer between the lateral portion of the control gate and the semiconductor body, wherein the third insulating layer is the same thickness as the second insulating layer.

11. The device according to claim 1, wherein

a vertical thickness of the first insulating layer is about 7.5 nm,

a vertical thickness of the second insulating layer is about 22 nm, and

a vertical thickness of the floating gate is about 100 nm.

12. The device according to claim 1, wherein the protruding portion of the floating gate has a width measured in a source-drain direction, and the floating gate has a width measured in the source-drain direction, wherein, to within 10%, the width of the protruding portion is one quarter of the width of the floating gate.

13. A method for writing logic data in a nonvolatile memory device that includes a memory plane arranged in a matrix array of rows and columns of memory cells, the rows being divided into memory words of a plurality of memory cells, the method comprising:

performing an erasing step for a first memory word, wherein all memory cells of the first memory word are turned on during the erasing step; and

performing a programming step for a second memory word, wherein memory cells of the second memory word not to be programmed are selected and memory cells of the memory word to be programmed are turned off, so that the memory cells of the memory word to be programmed are programmed in the memory cells of the second memory word not to be programmed are not programmed;

wherein each of the memory cells of the memory plane comprises

a source region and a drain region disposed in a semiconductor body,

a channel region disposed in the semiconductor body between the source region and the drain region,

a control gate, and

a floating gate disposed between the semiconductor body and the control gate;

wherein the floating gate includes a protruding portion that is located over the channel region between the source and drain regions and spaced therefrom, the protruding portion being separated from the channel region by a first insulating layer that is thinner than a second insulating layer that separates remaining portions of the floating gate from the channel region; and

wherein the control gate includes a lateral portion that extends beyond lateral ends of the floating gate and is vertically aligned with a portion of the channel region.

14. A memory cell comprising:

a source region disposed in a semiconductor body;

a drain region disposed in the semiconductor body and spaced from the source region in a source-drain direction by an intermediate region, the intermediate region being homogeneous along a top surface of the semiconductor body extending from the source region to the drain region;

a first insulating region overlying a middle portion of the intermediate region that is spaced from both the source region and the drain region along the source-drain direction;

a second insulating region having a first portion overlying the intermediate region between the middle portion of the intermediate region and the source region and having a second portion overlying the intermediate region between the middle portion of the intermediate region and the drain region, wherein

the first portion extends along the source-drain direction from the middle portion to the source region,

the second portion extends along the source-drain direction from the middle portion to the drain region, and

the second insulating region is thicker than the first insulating region;

a floating gate having a protruding portion that overlies the first insulating region, a first laterally extending portion that overlies the second insulating region in a direction of the source region, and a second laterally extending portion that overlies the second insulating region in a direction of the drain region; and

a control gate overlying the floating gate.

15. The memory cell according to claim 14, wherein the floating gate is laterally spaced from both the source region and the drain region and wherein the control gate extends beyond edges of the floating gate in the source-drain direction.

16. The memory cell according to claim 15, wherein portions of the control gate that extend beyond the edges of the floating gate in the source-drain direction form a selection structure that is configured to electrically isolate or electrically connect the source region and remaining portions of the memory cell.

17. The memory cell according to claim 14, further comprises a selection transistor that is laterally spaced from the floating gate and control gate.

18. The memory cell according to claim 17, wherein the selection transistor comprises a planar MOS transistor.

19. The memory cell according to claim 18, wherein the selection transistor comprises a control gate overlying and electrically connected to a floating gate.

20. The memory cell according to claim 17, wherein the selection transistor comprises a vertical MOS transistor extending from the source region into the semiconductor body.

21. The memory cell according to claim 14, wherein the protruding portion is substantially centered between the source region and the drain region.

22. The memory cell according to claim 21, wherein the floating gate and the control gate are substantially symmetric around a line that is perpendicular to the source-drain direction and extends through a center of the protruding portion in the source-drain direction.

23. The memory cell according to claim 14, further comprising a second floating gate overlying the semiconductor body and spaced from the floating gate in a direction perpendicular to the source-drain direction, the control gate overlying the second floating gate, wherein the second floating gate comprises a protruding portion that overlies an insulating layer having the same thickness as the first insulating region, a first laterally extending portion that overlies the second insulating region in the direction of the source region, and a second laterally extending portion that overlies the second insulating region in the direction of the drain region, the second floating gate being laterally spaced from both the source region and the drain region.

24. The memory cell according to claim 14, wherein the protruding portion of the floating gate has a width measured in a source-drain direction, and the floating gate has a width measured in the source-drain direction, wherein, to within 10%, the width of the protruding portion is one quarter of the width of the floating gate.