Method for fabricating semiconductor device including forming a dielectric layer on a structure having a height difference using ALD

• US 10,049,882 B1
• Filed: 01/25/2017
• Issued: 08/14/2018
• Est. Priority Date: 01/25/2017
• Status: Active Grant

• Current Assignee: NATA Semiconductor Materials Company Limited, Samsung Electronics Co. Ltd.
• Original Assignee: Dow Silicones Corporation (Dow, Inc.), Samsung Electronics Co. Ltd.
• Inventors: Chung, Won Woong, Hwang, Sun hye, Cho, Youn Joung, Choi, Jung Sik, Zhou, Xiaobing, Rekken, Brian David, Hwang, Byung Keun, Telgenhoff, Michael David
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US15/414,913
• Publication Number:
  US 20180211842A1
• Time in Patent Office: 566 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A method for fabricating a semiconductor device includes forming a structure with a height difference on a substrate and forming a dielectric layer structure on the structure using an atomic layer deposition (ALD) method. Forming the dielectric layer structure includes forming a first dielectric layer including silicon nitride on the structure with the height difference. Forming the first dielectric layer includes feeding a first gas including pentachlorodisilane (PCDS) or diisopropylamine pentachlorodisilane (DPDC) as a silicon precursor, and a second gas including nitrogen components into a chamber including the substrate such that the first dielectric layer is formed in situ on the structure having the height difference.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

forming a structure with a height difference on a substrate; and

forming a dielectric layer structure on the structure with the height difference using an atomic layer deposition (ALD) method,

wherein

forming the dielectric layer structure includes forming a first dielectric layer including silicon nitride on the structure with the height difference, wherein forming the first dielectric layer includes feeding a first gas including pentachlorodisilane (PCDS) or diisopropylamine pentachlorodisilane (DPDC) as a silicon precursor into a chamber including the substrate to form a silicon precursor layer having an atomic layer thickness on the structure with the height difference, and feeding a second gas including nitrogen into a chamber including the substrate, such that the second gas reacts with the silicon precursor layer to form a silicon nitride layer having an atomic layer thickness on the structure with the height difference.

2. The method as claimed in claim 1, wherein forming the first dielectric layer includes purging an unreacted portion of the first gas by feeding a first purge gas into the chamber and purging an unreacted portion of the second gas by feeding a second purge gas into the chamber.

3. The method as claimed in claim 1, wherein forming the first dielectric layer includes depositing the silicon precursor at a growth per cycle (GPC) rate of 0.8 Å

/cyc or higher at a temperature of 300°

C. to 400°

C.

4. The method as claimed in claim 3, wherein forming the first dielectric layer includes depositing the silicon precursor at a GPC rate of 0.9 Å

/cyc or higher at a temperature of 300°

C.

5. The method as claimed in claim 1, wherein forming the dielectric layer structure further includes forming a second dielectric layer including silicon oxide between the substrate and the first dielectric layer.

6. The method as claimed in claim 5, wherein:

the structure having the height difference includes global bit lines (GBLs), and

forming the dielectric layer structure further includes forming the second dielectric layer on the GLBs, and forming the first dielectric layer on the second dielectric layer.

7. The method as claimed in claim 5, wherein:

the structure having the height difference includes a charge storage layer, and

forming the dielectric layer structure further includes forming the second dielectric layer on the charge storage layer, and forming the first dielectric layer on the second dielectric layer.

8. The method as claimed in claim 1, wherein:

the structure having the height difference includes a gate, and

forming the first dielectric layer further includes forming the first dielectric layer on a sidewall of the gate.

9. The method as claimed in claim 1, wherein the second gas includes at least one of nitrogen (N₂) and ammonia (NH₃).

10. A method for fabricating a semiconductor device, the method comprising:

forming a structure on a substrate; and

forming a silicon nitride layer on the structure inside a chamber using an atomic layer deposition (ALD) method,

wherein forming the silicon nitride layer includes feeding a first gas including one of pentachlorodisilane (PCDS) and diisopropylaminopentachlorodisilane (DPDC) as a silicon precursor into the chamber to form a silicon precursor layer having an atomic layer thickness on the structure, purging an unreacted portion of the first gas by feeding a first purge gas into the chamber, feeding a second gas including nitrogen into the chamber such that the second gas reacts with the silicon precursor layer to form a silicon nitride film having an atomic layer thickness on the structure, and purging an unreacted portion of the second gas by feeding a second purge gas into the chamber.

11. The method as claimed in claim 10, wherein forming the silicon nitride layer includes forming first and second gate patterns on the substrate, forming an insulating layer pattern to cover the first and second gate patterns, forming a trench in the insulating layer pattern between the first and second gate patterns, and forming the silicon nitride layer on a sidewall of the trench.

12. The method as claimed in claim 10, wherein the structure is a trench having an aspect ratio of 10 or greater.

13. The method as claimed in claim 10, further comprising-etching the structure using the silicon nitride layer as a mask layer.

14. The method as claimed in claim 10, further comprising depositing the silicon precursor at a temperature that is 300°

C. or greater and less than 350°

C.

15. The method as claimed in claim 10, further comprising increasing a thickness of the silicon nitride layer by repeatedly performing forming the silicon nitride layer.

16. A method of forming a dielectric layer on a target object by atomic layer deposition, the target object containing at least one structural feature having a sidewall, the method comprising:

feeding a first gas including pentachlorodisilane (PCDS) or diisopropylamine pentachlorodisilane (DPDC) into a chamber including the target object to form a silicon precursor layer having an atomic layer thickness on the target object;

feeding a first purge gas into the chamber to purge an unreacted portion of the first gas from the chamber;

feeding a second gas into the chamber, the second gas including nitrogen, such that the second gas reacts with the silicon precursor layer to form a silicon nitride layer having an atomic layer thickness on the target object;

feeding a second purge gas into the chamber to purge an unreacted portion of the second gas from the chamber; and

repeating feeding the first gas, feeding the first purge gas, feeding the second gas and feeding the second purge gas to form the dielectric layer to include a silicon nitride layer having greater than an atomic layer thickness.

17. The method as claimed in claim 16, further including at least one of:

forming a silicon oxide layer on the target object before forming the silicon nitride layer having an atomic layer thickness, or

forming a silicon oxide layer on the formed dielectric layer including the silicon nitride layer having greater than an atomic layer thickness.

18. The method as claimed in claim 16, wherein the structural feature having a sidewall is a trench or recess having an aspect ratio of 10 or greater.

19. The method as claimed in claim 16, wherein forming the dielectric layer is carried out in the chamber at a temperature of 300°

C. to 400°

C.

20. The method as claimed in claim 16, further including performing a thermal treatment on the formed dielectric layer at a temperature of about 850°

C. to about 1,050°

C.