Method of making semiconductor structure having contact plug

• US 10,049,929 B2
• Filed: 01/28/2016
• Issued: 08/14/2018
• Est. Priority Date: 12/05/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hung, Ching-Wen, Huang, Chih-Sen, Tsao, Po-Chao, Chen, Chieh-Te
• Primary Examiner(s): Nguyen, Duy T
• Application Number:
  US15/008,453
• Publication Number:
  US 20160141207A1
• Time in Patent Office: 929 Days
• Field of Search: 438300, 438286, 438299, 438622, 438629
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7843 : the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 : the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.

Claims

1. A method of forming a semiconductor structure having at least a contact plug, comprising:

providing a substrate;

forming a transistor on the substrate, wherein the transistor comprises a gate and a source/drain region;

forming a dielectric layer on the substrate, wherein the transistor is disposed in the dielectric layer;

forming a first inter-layer dielectric (ILD) layer on the dielectric layer and the transistor, wherein a bottom surface of the first ILD is leveled with a top surface of the gate;

forming a first contact plug in the first ILD layer to electrically connect the source/drain region, wherein a top surface of the first contact plug is higher than a top surface of the gate, and wherein the top surface of the first contact plug is level with a top surface of the first ILD layer;

forming a second ILD layer on the first ILD layer; and

forming a second contact plug in the second ILD layer to electrically connect the first contact plug, and a third contact plug in the first ILD layer and the second ILD layer to electrically connect the gate, wherein a portion of the first ILD layer contacts the top surface of the gate between the first contact plug and the third contact plug, and wherein the first ILD layer is a single layer structure.

2. The method of forming the semiconductor structure having the at least a contact plug as in claim 1, wherein the step of forming the second contact plug and the third contact plug comprises:

forming a second opening in the second ILD layer to expose the first contact plug;

forming a third opening in the second ILD layer and the first ILD layer to expose the gate; and

filling a second metal layer in the second opening and the third opening.

3. The method of forming the semiconductor structure having the at least a contact plug as in claim 2, wherein the second opening is formed and then the third opening is formed.

4. The method of forming the semiconductor structure having the at least a contact plug as in claim 2, wherein the third opening is formed and then the second opening is formed.

5. The method of forming the semiconductor structure having the at least a contact plug as in claim 1, wherein step of forming the first contact plug comprises:

forming a first opening in the first ILD layer to expose the source/drain region;

filling a first metal layer in the first opening; and

performing a planarization process.

6. The method of forming the semiconductor structure having the at least a contact plug as in claim 5, wherein after the planarization process, there is still the first ILD layer having a predetermined thickness on the top surface of the gate.

7. The method of forming the semiconductor structure having the at least a contact plug as in claim 6, wherein the predetermined thickness is greater than 100 angstroms.

8. The method of forming the semiconductor structure having the at least a contact plug as in claim 5, wherein before filling the first metal layer in the first opening, further comprises performing a salicidation process to form a silicide layer on the source/drain region exposed by the first opening.

9. The method of forming the semiconductor structure having the at least a contact plug as in claim 1, wherein the first contact plug has a stress.

10. The method of forming the semiconductor structure having the at least a contact plug as in claim 1, further comprises forming an etch stop layer between the first ILD layer and the second ILD layer.

11. The method of forming the semiconductor structure having the at least a contact plug as in claim 1, wherein a bottom surface of the second contact plug is level with a top surface of the first ILD layer.

12. The method of forming the semiconductor structure having the at least a contact plug as in claim 1, wherein a top surface of the dielectric layer is leveled with a top surface of the gate.